Merge branch 'master' of https://lxsd.femto-st.fr/gitlab/jfriedt/ifcs2018-article

Arthur HUGEAT
2 parents 48d886be99 0494f3f5bb
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biblio.bib
ifcs2018_proceeding.tex
@@ -185,4 +185,12 @@
   year={2002},
   publisher={Elsevier}
 }
+
+@article{andrich2018high,
+  title={High-Precision Measurement of Sine and Pulse Reference Signals Using Software-Defined Radio},
+  author={Andrich, Carsten and Ihlow, Alexander and Bauer, Julia and Beuster, Niklas and Del Galdo, Giovanni},
+  journal={IEEE Transactions on Instrumentation and Measurement},
+  year={2018},
+  publisher={IEEE}
+}
+% JMF : revoir l'abstract : on y avait mis le Zynq7010 de la redpitaya en montrant
+%   comment optimiser les perfs a surface finie. Ici aussi on tombait dans le cas ou`
+%   la solution a 1 seul FIR n'etait simplement pas synthetisable => fusionner les deux
+%   contributions pour le papier TUFFC
+
 \documentclass[a4paper,conference]{IEEEtran/IEEEtran}
 \usepackage{graphicx,color,hyperref}
 \usepackage{amsfonts}
@@ -67,7 +72,7 @@
 the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as
 well as the generation of the frequency sum signal in addition to the frequency difference.
 These unwanted spectral characteristics must be rejected before decimating the data stream
-for the phase noise spectral characterization. The characteristics introduced between the
+for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the
 downconverter
 and the decimation processing blocks are core characteristics of an oscillator characterization
 system, and must reject out-of-band signals below the targeted phase noise -- typically in the
@@ -92,7 +97,7 @@
 defining the coefficients and the sample size. For this reason, and because we consider pipeline
 processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency
 signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
-the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
+the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level.
 Since latency is not an issue in a openloop phase noise characterization instrument, the large
 numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
 is not considered as an issue as would be in a closed loop system.
@@ -203,8 +208,8 @@
   \end{cases}
   \label{model-FIR}
 \end{align}
-To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
-is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
+To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the stopband rejection dependence with $N_i$ and $C_i$, $\mathcal{A}$
+is a theoretical area occupation of the processing block on the FPGA as discussed earlier, and $\Delta_i$ is the total rejection for the current stage $i$.
 Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
 on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
 incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
  
@@ -223,13 +228,17 @@
 \end{figure}
  
 The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below
-a user-defined threshold. The MILP solver is allowed to choose the number of successive
+a user-defined threshold, or aims at minimizing the area needed to reach a given rejection ($\min(S_q)$ in
+the forthcoming discussion, Eqs. \ref{cstr_size} and \ref{cstr_rejection}).
+The MILP solver is allowed to choose the number of successive
 filters, within an upper bound. The last problem is to model the noise rejection. Since filter
 noise rejection capability is not modeled with linear equations, a look-up-table is generated
 for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each
-one of these conditions, the low-pass filter rejection defined as the mean power between
-half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response
-of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum
+one of these conditions, the low-pass filter rejection is stored as computed by the frequency response
+of the digital filter (Fig. \ref{noise-rejection}). Various rejection criteria have been investigated,
+including mean value of the stopband response, median value of the stopband response, or as finally
+selected, maximum value in the stopband. An intuitive analysis of the chart of Fig. \ref{noise-rejection}
+hints at an optimum
 set of tap length and number of bit for representing the coefficients along the line of the pyramidal
 shaped rejection capability function.
  
@@ -303,7 +312,7 @@
  
 The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
 We have considered a set of resources representative of the hardware platform we work on,
-Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
+Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results reported in
 Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
 the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
 filters fit in the available resources. However, in all cases the DSP resources are fully
...	...	@@ -185,4 +185,12 @@
185	185	year={2002},
186	186	publisher={Elsevier}
187	187	}
	188	+
	189	+@article{andrich2018high,
	190	+ title={High-Precision Measurement of Sine and Pulse Reference Signals Using Software-Defined Radio},
	191	+ author={Andrich, Carsten and Ihlow, Alexander and Bauer, Julia and Beuster, Niklas and Del Galdo, Giovanni},
	192	+ journal={IEEE Transactions on Instrumentation and Measurement},
	193	+ year={2018},
	194	+ publisher={IEEE}
	195	+}
	1	+% JMF : revoir l'abstract : on y avait mis le Zynq7010 de la redpitaya en montrant
	2	+% comment optimiser les perfs a surface finie. Ici aussi on tombait dans le cas ou`
	3	+% la solution a 1 seul FIR n'etait simplement pas synthetisable => fusionner les deux
	4	+% contributions pour le papier TUFFC
	5	+
1	6	\documentclass[a4paper,conference]{IEEEtran/IEEEtran}
2	7	\usepackage{graphicx,color,hyperref}
3	8	\usepackage{amsfonts}
...	...	@@ -67,7 +72,7 @@
67	72	the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as
68	73	well as the generation of the frequency sum signal in addition to the frequency difference.
69	74	These unwanted spectral characteristics must be rejected before decimating the data stream
70		-for the phase noise spectral characterization. The characteristics introduced between the
	75	+for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the
71	76	downconverter
72	77	and the decimation processing blocks are core characteristics of an oscillator characterization
73	78	system, and must reject out-of-band signals below the targeted phase noise -- typically in the
...	...	@@ -92,7 +97,7 @@
92	97	defining the coefficients and the sample size. For this reason, and because we consider pipeline
93	98	processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency
94	99	signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
95		-the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
	100	+the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level.
96	101	Since latency is not an issue in a openloop phase noise characterization instrument, the large
97	102	numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
98	103	is not considered as an issue as would be in a closed loop system.
...	...	@@ -203,8 +208,8 @@
203	208	\end{cases}
204	209	\label{model-FIR}
205	210	\end{align}
206		-To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
207		-is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
	211	+To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the stopband rejection dependence with $N_i$ and $C_i$, $\mathcal{A}$
	212	+is a theoretical area occupation of the processing block on the FPGA as discussed earlier, and $\Delta_i$ is the total rejection for the current stage $i$.
208	213	Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
209	214	on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
210	215	incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
211	216
...	...	@@ -223,13 +228,17 @@
223	228	\end{figure}
224	229
225	230	The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below
226		-a user-defined threshold. The MILP solver is allowed to choose the number of successive
	231	+a user-defined threshold, or aims at minimizing the area needed to reach a given rejection ($\min(S_q)$ in
	232	+the forthcoming discussion, Eqs. \ref{cstr_size} and \ref{cstr_rejection}).
	233	+The MILP solver is allowed to choose the number of successive
227	234	filters, within an upper bound. The last problem is to model the noise rejection. Since filter
228	235	noise rejection capability is not modeled with linear equations, a look-up-table is generated
229	236	for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each
230		-one of these conditions, the low-pass filter rejection defined as the mean power between
231		-half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response
232		-of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum
	237	+one of these conditions, the low-pass filter rejection is stored as computed by the frequency response
	238	+of the digital filter (Fig. \ref{noise-rejection}). Various rejection criteria have been investigated,
	239	+including mean value of the stopband response, median value of the stopband response, or as finally
	240	+selected, maximum value in the stopband. An intuitive analysis of the chart of Fig. \ref{noise-rejection}
	241	+hints at an optimum
233	242	set of tap length and number of bit for representing the coefficients along the line of the pyramidal
234	243	shaped rejection capability function.
235	244
...	...	@@ -303,7 +312,7 @@
303	312
304	313	The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
305	314	We have considered a set of resources representative of the hardware platform we work on,
306		-Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
	315	+Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results reported in
307	316	Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
308	317	the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
309	318	filters fit in the available resources. However, in all cases the DSP resources are fully