Correction des notations.

Arthur HUGEAT
1 parent 9f4af76a79
Showing 1 changed file with 12 additions and 13 deletions Side-by-side Diff
ifcs2018_proceeding.tex
@@ -166,11 +166,10 @@
 resources indeed matches the definition of a classical optimization problem.
  
 Specifically the degrees of freedom when addressing the problem of replacing the single monolithic
-FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$,
-the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ representing
-the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage,
+FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$ and
+the number of bits $C_i$ representing the coefficients. Because each FIR in the chain is fed the output of the previous stage,
 the optimization of the complete processing chain within a constrained resource environment is not
-trivial. The resource occupation of a FIR filter is considered as $(D_i+C_i) \times N_i$ which is
+trivial. The resource occupation of a FIR filter is considered as $C_i \times N_i$ which is
 the number of bits needed in a worst case condition to represent the output of the FIR. Such an
 occupied area estimate assumes that the number of gates scales as the number of bits and the number
 of coefficients, but does not account for the detailed implementation of the hardware. Indeed,
@@ -199,7 +198,7 @@
 \begin{align}
   \begin{cases}
     \mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\
-    \mathcal{A}_i &= N_i * C_i + D_i\
+    \mathcal{A}_i &= N_i * C_i\
     \Delta_i &= \Delta _{i-1} + \mathcal{P}_i
   \end{cases}
   \label{model-FIR}
@@ -248,13 +247,13 @@
 \begin{align*}
 \mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\
 & \text{ $p$ is the number of different filters} \\
-C(i) & \text{ % Constant to let the
-number of coefficients %} \\ & \text{
-for filter $i$}\\
-\pi_C(i) & \text{ % Constant to let the
-number of bits of %}\\ & \text{
-each coefficient for filter $i$}\\
-\mathcal{A}_{\max} & \text{ Total space available inside the FPGA}
+% N(i) & \text{ % Constant to let the
+% number of coefficients %} \\ & \text{
+% for filter $i$}\\
+% C(i) & \text{ % Constant to let the
+% number of bits of %}\\ & \text{
+% each coefficient for filter $i$}\\
+\mathcal{S}_{\max} & \text{ Total space available inside the FPGA}
 \end{align*}
 \paragraph{Constraints}
 \begin{align}
@@ -284,7 +283,7 @@
  
 The MILP solver provides a solution to the problem by selecting a series of small FIR with
 increasing number of bits representing data and coefficients as well as an increasing number
-of coefficients, instead of a single monolithic filter. 
+of coefficients, instead of a single monolithic filter.
  
 \begin{figure}[h!tb]
 % \includegraphics[width=\linewidth]{images/compare-fir.pdf}
...	...	@@ -166,11 +166,10 @@
166	166	resources indeed matches the definition of a classical optimization problem.
167	167
168	168	Specifically the degrees of freedom when addressing the problem of replacing the single monolithic
169		-FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$,
170		-the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ representing
171		-the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage,
	169	+FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$ and
	170	+the number of bits $C_i$ representing the coefficients. Because each FIR in the chain is fed the output of the previous stage,
172	171	the optimization of the complete processing chain within a constrained resource environment is not
173		-trivial. The resource occupation of a FIR filter is considered as $(D_i+C_i) \times N_i$ which is
	172	+trivial. The resource occupation of a FIR filter is considered as $C_i \times N_i$ which is
174	173	the number of bits needed in a worst case condition to represent the output of the FIR. Such an
175	174	occupied area estimate assumes that the number of gates scales as the number of bits and the number
176	175	of coefficients, but does not account for the detailed implementation of the hardware. Indeed,
...	...	@@ -199,7 +198,7 @@
199	198	\begin{align}
200	199	\begin{cases}
201	200	\mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\
202		- \mathcal{A}_i &= N_i * C_i + D_i\
	201	+ \mathcal{A}_i &= N_i * C_i\
203	202	\Delta_i &= \Delta _{i-1} + \mathcal{P}_i
204	203	\end{cases}
205	204	\label{model-FIR}
...	...	@@ -248,13 +247,13 @@
248	247	\begin{align*}
249	248	\mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\
250	249	& \text{ $p$ is the number of different filters} \\
251		-C(i) & \text{ % Constant to let the
252		-number of coefficients %} \\ & \text{
253		-for filter $i$}\\
254		-\pi_C(i) & \text{ % Constant to let the
255		-number of bits of %}\\ & \text{
256		-each coefficient for filter $i$}\\
257		-\mathcal{A}_{\max} & \text{ Total space available inside the FPGA}
	250	+% N(i) & \text{ % Constant to let the
	251	+% number of coefficients %} \\ & \text{
	252	+% for filter $i$}\\
	253	+% C(i) & \text{ % Constant to let the
	254	+% number of bits of %}\\ & \text{
	255	+% each coefficient for filter $i$}\\
	256	+\mathcal{S}_{\max} & \text{ Total space available inside the FPGA}
258	257	\end{align*}
259	258	\paragraph{Constraints}
260	259	\begin{align}
...	...	@@ -284,7 +283,7 @@
284	283
285	284	The MILP solver provides a solution to the problem by selecting a series of small FIR with
286	285	increasing number of bits representing data and coefficients as well as an increasing number
287		-of coefficients, instead of a single monolithic filter.
	286	+of coefficients, instead of a single monolithic filter.
288	287
289	288	\begin{figure}[h!tb]
290	289	% \includegraphics[width=\linewidth]{images/compare-fir.pdf}