corrections mineures

jfriedt
1 parent 9de4320e23
Showing 1 changed file with 18 additions and 9 deletions Side-by-side Diff
ifcs2018_proceeding.tex
+% JMF : revoir l'abstract : on y avait mis le Zynq7010 de la redpitaya en montrant
+%   comment optimiser les perfs a surface finie. Ici aussi on tombait dans le cas ou`
+%   la solution a 1 seul FIR n'etait simplement pas synthetisable => fusionner les deux
+%   contributions pour le papier TUFFC
+
 \documentclass[a4paper,conference]{IEEEtran/IEEEtran}
 \usepackage{graphicx,color,hyperref}
 \usepackage{amsfonts}
@@ -92,7 +97,7 @@
 defining the coefficients and the sample size. For this reason, and because we consider pipeline
 processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency
 signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
-the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
+the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level.
 Since latency is not an issue in a openloop phase noise characterization instrument, the large
 numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
 is not considered as an issue as would be in a closed loop system.
  
@@ -199,13 +204,13 @@
 \begin{align}
   \begin{cases}
     \mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\
-    \mathcal{A}_i &= N_i * C_i + D_i\
+    \mathcal{A}_i &= N_i \times (C_i + D_i)\
     \Delta_i &= \Delta _{i-1} + \mathcal{P}_i
   \end{cases}
   \label{model-FIR}
 \end{align}
-To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
-is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
+To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the stopband rejection dependence with $N_i$ and $C_i$, $\mathcal{A}$
+is a theoretical area occupation of the processing block on the FPGA as discussed earlier, and $\Delta_i$ is the total rejection for the current stage $i$.
 Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
 on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
 incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
  
@@ -224,13 +229,17 @@
 \end{figure}
  
 The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below
-a user-defined threshold. The MILP solver is allowed to choose the number of successive
+a user-defined threshold, or aims at minimizing the area needed to reach a given rejection ($\min(S_q)$ in
+the forthcoming discussion, Eqs. \ref{cstr_size} and \ref{cstr_rejection}). 
+The MILP solver is allowed to choose the number of successive
 filters, within an upper bound. The last problem is to model the noise rejection. Since filter
 noise rejection capability is not modeled with linear equations, a look-up-table is generated
 for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each
-one of these conditions, the low-pass filter rejection defined as the mean power between
-half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response
-of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum
+one of these conditions, the low-pass filter rejection is stored as computed by the frequency response
+of the digital filter (Fig. \ref{noise-rejection}). Various rejection criteria have been investigated,
+including mean value of the stopband response, median value of the stopband response, or as finally
+selected, maximum value in the stopband. An intuitive analysis of the chart of Fig. \ref{noise-rejection} 
+hints at an optimum
 set of tap length and number of bit for representing the coefficients along the line of the pyramidal
 shaped rejection capability function.
  
@@ -304,7 +313,7 @@
  
 The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
 We have considered a set of resources representative of the hardware platform we work on,
-Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
+Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results reported in
 Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
 the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
 filters fit in the available resources. However, in all cases the DSP resources are fully
	1	+% JMF : revoir l'abstract : on y avait mis le Zynq7010 de la redpitaya en montrant
	2	+% comment optimiser les perfs a surface finie. Ici aussi on tombait dans le cas ou`
	3	+% la solution a 1 seul FIR n'etait simplement pas synthetisable => fusionner les deux
	4	+% contributions pour le papier TUFFC
	5	+
1	6	\documentclass[a4paper,conference]{IEEEtran/IEEEtran}
2	7	\usepackage{graphicx,color,hyperref}
3	8	\usepackage{amsfonts}
...	...	@@ -92,7 +97,7 @@
92	97	defining the coefficients and the sample size. For this reason, and because we consider pipeline
93	98	processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency
94	99	signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
95		-the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
	100	+the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level.
96	101	Since latency is not an issue in a openloop phase noise characterization instrument, the large
97	102	numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
98	103	is not considered as an issue as would be in a closed loop system.
99	104
...	...	@@ -199,13 +204,13 @@
199	204	\begin{align}
200	205	\begin{cases}
201	206	\mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\
202		- \mathcal{A}_i &= N_i * C_i + D_i\
	207	+ \mathcal{A}_i &= N_i \times (C_i + D_i)\
203	208	\Delta_i &= \Delta _{i-1} + \mathcal{P}_i
204	209	\end{cases}
205	210	\label{model-FIR}
206	211	\end{align}
207		-To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
208		-is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
	212	+To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the stopband rejection dependence with $N_i$ and $C_i$, $\mathcal{A}$
	213	+is a theoretical area occupation of the processing block on the FPGA as discussed earlier, and $\Delta_i$ is the total rejection for the current stage $i$.
209	214	Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
210	215	on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
211	216	incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
212	217
...	...	@@ -224,13 +229,17 @@
224	229	\end{figure}
225	230
226	231	The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below
227		-a user-defined threshold. The MILP solver is allowed to choose the number of successive
	232	+a user-defined threshold, or aims at minimizing the area needed to reach a given rejection ($\min(S_q)$ in
	233	+the forthcoming discussion, Eqs. \ref{cstr_size} and \ref{cstr_rejection}).
	234	+The MILP solver is allowed to choose the number of successive
228	235	filters, within an upper bound. The last problem is to model the noise rejection. Since filter
229	236	noise rejection capability is not modeled with linear equations, a look-up-table is generated
230	237	for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each
231		-one of these conditions, the low-pass filter rejection defined as the mean power between
232		-half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response
233		-of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum
	238	+one of these conditions, the low-pass filter rejection is stored as computed by the frequency response
	239	+of the digital filter (Fig. \ref{noise-rejection}). Various rejection criteria have been investigated,
	240	+including mean value of the stopband response, median value of the stopband response, or as finally
	241	+selected, maximum value in the stopband. An intuitive analysis of the chart of Fig. \ref{noise-rejection}
	242	+hints at an optimum
234	243	set of tap length and number of bit for representing the coefficients along the line of the pyramidal
235	244	shaped rejection capability function.
236	245
...	...	@@ -304,7 +313,7 @@
304	313
305	314	The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
306	315	We have considered a set of resources representative of the hardware platform we work on,
307		-Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
	316	+Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results reported in
308	317	Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
309	318	the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
310	319	filters fit in the available resources. However, in all cases the DSP resources are fully