Commit bee7a1f72b9b252f21a313b52975359e96db6f95

Authored by Arthur HUGEAT
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ifcs2018_proceeding.tex
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137 137 follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards}
138 138 in which basic blocks are defined and characterized before being assembled \cite{hide}
139 139 in a complete processing chain. In our case, assembling the filter blocks is a simpler block
140   -combination process since we assume a single value to be processed and a single value to be
  140 +combination process since we assume a single value to be processed and a single value to be
141 141 generated at each clock cycle. The FIR filters will not be considered to decimate in the
142 142 current implementation: the decimation is assumed to be located after the FIR cascade at the
143 143 moment.
... ... @@ -168,7 +168,7 @@
168 168 the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ representing
169 169 the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage,
170 170 the optimization of the complete processing chain within a constrained resource environment is not
171   -trivial. The resource occupation of a FIR filter is considered as $D_i+C_i \times N_i)$ which is
  171 +trivial. The resource occupation of a FIR filter is considered as $(D_i+C_i) \times N_i$ which is
172 172 the number of bits needed in a worst case condition to represent the output of the FIR. Such an
173 173 occupied area estimate assumes that the number of gates scales as the number of bits and the number
174 174 of coefficients, but does not account for the detailed implementation of the hardware. Indeed,
175 175  
176 176  
... ... @@ -202,12 +202,12 @@
202 202 \label{model-FIR}
203 203 \end{align}
204 204 To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
205   -is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
  205 +is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
206 206 Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
207   -on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
208   -incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
  207 +on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
  208 +incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
209 209 Hence, amongst various criteria including the mean or median value of the FIR response in the stopband, we have designed
210   -a criterion aimed at avoiding ripples on passband and considering the maximum of the FIR spectral response in the stopband
  210 +a criterion aimed at avoiding ripples on passband and considering the maximum of the FIR spectral response in the stopband
211 211 (Fig. \ref{rejection-shape}). The bandpass criterion is defined as the sum of the absolute values of the spectral response
212 212 in the bandpass, reminiscent of a standard deviation of the spectral response: this criterion must be minimized to avoid
213 213 ripples in the passband. The stopband transfer function maximum must also be minimized in order to improve the filter
214 214  
... ... @@ -242,11 +242,11 @@
242 242 \begin{align*}
243 243 \mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\
244 244 & \text{ $p$ is the number of different filters} \\
245   -C(i) & \text{ % Constant to let the
246   -number of coefficients %} \\ & \text{
  245 +C(i) & \text{ % Constant to let the
  246 +number of coefficients %} \\ & \text{
247 247 for filter $i$}\\
248   -\pi_C(i) & \text{ % Constant to let the
249   -number of bits of %}\\ & \text{
  248 +\pi_C(i) & \text{ % Constant to let the
  249 +number of bits of %}\\ & \text{
250 250 each coefficient for filter $i$}\\
251 251 \mathcal{A}_{\max} & \text{ Total space available inside the FPGA}
252 252 \end{align*}
253 253  
... ... @@ -256,11 +256,11 @@
256 256 1 \leq j \leq q & \text{ $q$ is the max of filter stage} \nonumber \\
257 257 \forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \nonumber\\
258 258 \mathcal{S}_0 = 0 & \text{ initial occupation} \nonumber\\
259   -\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \forall i, x_{i,j} \times \mathcal{A}_i \label{cstr_size} \
  259 +\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{A}_i)} \label{cstr_size} \
260 260 \mathcal{S} \leq \mathcal{S}_{\max}\nonumber \\
261 261 \mathcal{N}_0 = 0 & \text{ initial rejection}\nonumber\\
262   -\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \forall i, x_{i,j} \times \mathcal{R}_i \label{cstr_rejection} \\
263   -\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\
  262 +\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{R}_i)} \label{cstr_rejection} \\
  263 +\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\
264 264 & \text{ (e.g. 160~dB here)}\nonumber\\\nonumber
265 265 \end{align}
266 266 \paragraph{Goal}
... ... @@ -316,7 +316,7 @@
316 316 The coefficients of a single monolithic filter are computed as the impulse response
317 317 of the filter transfer function, and practically approximated by a multitude of methods
318 318 including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing
319   -(Matlab's {\tt fir1} function).
  319 +(Matlab's {\tt fir1} function).
320 320  
321 321 \begin{figure}[h!tb]
322 322 \includegraphics[width=\linewidth]{images/fir1-vs-firls}