diff --git a/ifcs2018_proceeding.tex b/ifcs2018_proceeding.tex
index e004237..967ffd8 100644
--- a/ifcs2018_proceeding.tex
+++ b/ifcs2018_proceeding.tex
@@ -137,7 +137,7 @@ and tap length, as will be shown in the next section. Indeed, our development st
 follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards}
 in which basic blocks are defined and characterized before being assembled \cite{hide}
 in a complete processing chain. In our case, assembling the filter blocks is a simpler block
-combination process since we assume a single value to be processed and a single value to be 
+combination process since we assume a single value to be processed and a single value to be
 generated at each clock cycle. The FIR filters will not be considered to decimate in the
 current implementation: the decimation is assumed to be located after the FIR cascade at the
 moment.
@@ -168,7 +168,7 @@ FIR with a cascade of optimized filters are the number of coefficients $N_i$ of
 the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ representing
 the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage,
 the optimization of the complete processing chain within a constrained resource environment is not
-trivial. The resource occupation of a FIR filter is considered as $D_i+C_i \times N_i)$ which is
+trivial. The resource occupation of a FIR filter is considered as $(D_i+C_i) \times N_i$ which is
 the number of bits needed in a worst case condition to represent the output of the FIR. Such an
 occupied area estimate assumes that the number of gates scales as the number of bits and the number
 of coefficients, but does not account for the detailed implementation of the hardware. Indeed,
@@ -202,12 +202,12 @@ Following these considerations, the model is expressed as:
   \label{model-FIR}
 \end{align}
 To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
-is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$. 
+is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
 Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
-on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an  
-incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements. 
+on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
+incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
 Hence, amongst various criteria including the mean or median value of the FIR response in the stopband, we have designed
-a criterion aimed at avoiding ripples on passband and considering the maximum of the FIR spectral response in the stopband 
+a criterion aimed at avoiding ripples on passband and considering the maximum of the FIR spectral response in the stopband
 (Fig. \ref{rejection-shape}). The bandpass criterion is defined as the sum of the absolute values of the spectral response
 in the bandpass, reminiscent of a standard deviation of the spectral response: this criterion must be minimized to avoid
 ripples in the passband. The stopband transfer function maximum must also be minimized in order to improve the filter
@@ -242,11 +242,11 @@ x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a given filter} \\
 \begin{align*}
 \mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\
 & \text{ $p$ is the number of different filters} \\
-C(i) & \text{ % Constant to let the 
-number of coefficients %} \\ & \text{ 
+C(i) & \text{ % Constant to let the
+number of coefficients %} \\ & \text{
 for filter $i$}\\
-\pi_C(i) & \text{ % Constant to let the 
-number of bits of %}\\ & \text{ 
+\pi_C(i) & \text{ % Constant to let the
+number of bits of %}\\ & \text{
 each coefficient for filter $i$}\\
 \mathcal{A}_{\max} & \text{ Total space available inside the FPGA}
 \end{align*}
@@ -256,11 +256,11 @@ each coefficient for filter $i$}\\
 1 \leq j \leq q & \text{ $q$ is the max of filter stage} \nonumber \\
 \forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \nonumber\\
 \mathcal{S}_0 = 0 & \text{ initial occupation} \nonumber\\
-\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \forall i, x_{i,j} \times \mathcal{A}_i \label{cstr_size} \\
+\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{A}_i)} \label{cstr_size} \\
 \mathcal{S} \leq \mathcal{S}_{\max}\nonumber \\
 \mathcal{N}_0 = 0 & \text{ initial rejection}\nonumber\\
-\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \forall i, x_{i,j} \times \mathcal{R}_i \label{cstr_rejection} \\
-\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\ 
+\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{R}_i)} \label{cstr_rejection} \\
+\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\
 & \text{ (e.g. 160~dB here)}\nonumber\\\nonumber
 \end{align}
 \paragraph{Goal}
@@ -316,7 +316,7 @@ FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline
 The coefficients of a single monolithic filter are computed as the impulse response
 of the filter transfer function, and practically approximated by a multitude of methods
 including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing
-(Matlab's {\tt fir1} function). 
+(Matlab's {\tt fir1} function).
 
 \begin{figure}[h!tb]
 \includegraphics[width=\linewidth]{images/fir1-vs-firls}