Commit 9513b431026879f907155817be80bff018624287
1 parent
67ebe1295f
Exists in
master
remplacement Tab1 par la version du poster
Showing 1 changed file with 13 additions and 7 deletions Side-by-side Diff
ifcs2018_proceeding.tex
| ... | ... | @@ -307,7 +307,7 @@ |
| 307 | 307 | Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on |
| 308 | 308 | Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to |
| 309 | 309 | the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10 |
| 310 | -filters fits in the available resources. However, in all cases the DSP resources are fully | |
| 310 | +filters fit in the available resources. However, in all cases the DSP resources are fully | |
| 311 | 311 | used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software, |
| 312 | 312 | implementing the design fails due to the excessive resource usage preventing routing the signals |
| 313 | 313 | on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization |
| ... | ... | @@ -320,12 +320,18 @@ |
| 320 | 320 | identified as optimal by the MILP solver within a finite resource criterion. The last line refers |
| 321 | 321 | to available resources on a Zynq-7020 as found on the Zedboard.} |
| 322 | 322 | \begin{center} |
| 323 | -\begin{tabular}{|c|cccc|}\hline | |
| 324 | -FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline | |
| 325 | -1 (monolithic) & 1 & 76183 & 220 & -162 \\ | |
| 326 | -5 & 5 & 18597 & 220 & -160 \\ | |
| 327 | -10 & 8 & 24729 & 220 & -161 \\\hline\hline | |
| 328 | -\textbf{Zynq 7020} & \textbf{420} & \textbf{53200} & \textbf{220} & \\\hline | |
| 323 | +%\begin{tabular}{|c|cccc|}\hline | |
| 324 | +%FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline | |
| 325 | +%1 (monolithic) & 1 & 76183 & 220 & -162 \\ | |
| 326 | +%5 & 5 & 18597 & 220 & -160 \\ | |
| 327 | +%10 & 8 & 24729 & 220 & -161 \\\hline\hline | |
| 328 | +%\textbf{Zynq 7020} & \textbf{420} & \textbf{53200} & \textbf{220} & \\\hline | |
| 329 | +\begin{tabular}{|c|ccccc|}\hline | |
| 330 | +FIR & BRAM36 & BRAM18 & LUT & DSP & rejection (dB)\\\hline\hline | |
| 331 | +1 (monolithic) & 1 & 0 & {\color{Red}76183} & 220 & -162 \\ | |
| 332 | +5 & 0 & 5 & {\color{Green}18597} & 220 & -160 \\ | |
| 333 | +10 & 0 & 8 & {\color{Green}24729} & 220 & -161 \\\hline\hline | |
| 334 | +\textbf{Zynq 7020} & \textbf{140} & \textbf{280} & \textbf{53200} & \textbf{220} & \\\hline | |
| 329 | 335 | \end{tabular} |
| 330 | 336 | \end{center} |
| 331 | 337 | %\vspace{-0.7cm} |