tentative de description du Tab1

jfriedt
1 parent 6f7c0de29f
Showing 1 changed file with 20 additions and 6 deletions Side-by-side Diff
ifcs2018_proceeding.tex
@@ -284,12 +284,7 @@
  
 The MILP solver provides a solution to the problem by selecting a series of small FIR with
 increasing number of bits representing data and coefficients as well as an increasing number
-of coefficients, instead of a single monolithic filter. Fig. \ref{compare-fir} exhibits the
-performance comparison between one solution and a monolithic FIR when selecting a cutoff
-frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the
-same space usage are provided as selected by the MILP solver. The FIR cascade provides improved
-rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to
-be tuned or compensated for.
+of coefficients, instead of a single monolithic filter. 
  
 \begin{figure}[h!tb]
 % \includegraphics[width=\linewidth]{images/compare-fir.pdf}
  
@@ -299,7 +294,26 @@
 \label{compare-fir}
 \end{figure}
  
+Fig. \ref{compare-fir} exhibits the
+performance comparison between one solution and a monolithic FIR when selecting a cutoff
+frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the
+same space usage are provided as selected by the MILP solver. The FIR cascade provides improved
+rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to
+be tuned or compensated for.
+
+
 The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
+We have considered a set of resources representative of the hardware platform we work on,
+Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
+Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
+the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
+filters fits in the available resources. However, in all cases the DSP resources are fully
+used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software,
+implementing the design fails due to the excessive resource usage preventing routing the signals
+on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization
+procedure by finding non-trivial solutions matching resource constraints, but on the other
+hand also illustrates the limitation of a model with an abstraction layer that does not account
+for the detailed architecture of the hardware.
  
 \begin{table}[h!tb]
 \caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade
...	...	@@ -284,12 +284,7 @@
284	284
285	285	The MILP solver provides a solution to the problem by selecting a series of small FIR with
286	286	increasing number of bits representing data and coefficients as well as an increasing number
287		-of coefficients, instead of a single monolithic filter. Fig. \ref{compare-fir} exhibits the
288		-performance comparison between one solution and a monolithic FIR when selecting a cutoff
289		-frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the
290		-same space usage are provided as selected by the MILP solver. The FIR cascade provides improved
291		-rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to
292		-be tuned or compensated for.
	287	+of coefficients, instead of a single monolithic filter.
293	288
294	289	\begin{figure}[h!tb]
295	290	% \includegraphics[width=\linewidth]{images/compare-fir.pdf}
296	291
...	...	@@ -299,7 +294,26 @@
299	294	\label{compare-fir}
300	295	\end{figure}
301	296
	297	+Fig. \ref{compare-fir} exhibits the
	298	+performance comparison between one solution and a monolithic FIR when selecting a cutoff
	299	+frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the
	300	+same space usage are provided as selected by the MILP solver. The FIR cascade provides improved
	301	+rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to
	302	+be tuned or compensated for.
	303	+
	304	+
302	305	The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
	306	+We have considered a set of resources representative of the hardware platform we work on,
	307	+Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
	308	+Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
	309	+the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
	310	+filters fits in the available resources. However, in all cases the DSP resources are fully
	311	+used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software,
	312	+implementing the design fails due to the excessive resource usage preventing routing the signals
	313	+on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization
	314	+procedure by finding non-trivial solutions matching resource constraints, but on the other
	315	+hand also illustrates the limitation of a model with an abstraction layer that does not account
	316	+for the detailed architecture of the hardware.
303	317
304	318	\begin{table}[h!tb]
305	319	\caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade