From 67ebe1295fab8ba8718abe2fc41a61ed265e7e7f Mon Sep 17 00:00:00 2001 From: jmfriedt Date: Sun, 20 May 2018 16:56:40 +0200 Subject: [PATCH] tentative de description du Tab1 --- ifcs2018_proceeding.tex | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/ifcs2018_proceeding.tex b/ifcs2018_proceeding.tex index 368a810..14485f5 100644 --- a/ifcs2018_proceeding.tex +++ b/ifcs2018_proceeding.tex @@ -284,12 +284,7 @@ plus the rejection of selected filter. The MILP solver provides a solution to the problem by selecting a series of small FIR with increasing number of bits representing data and coefficients as well as an increasing number -of coefficients, instead of a single monolithic filter. Fig. \ref{compare-fir} exhibits the -performance comparison between one solution and a monolithic FIR when selecting a cutoff -frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the -same space usage are provided as selected by the MILP solver. The FIR cascade provides improved -rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to -be tuned or compensated for. +of coefficients, instead of a single monolithic filter. \begin{figure}[h!tb] % \includegraphics[width=\linewidth]{images/compare-fir.pdf} @@ -299,7 +294,26 @@ with a cutoff frequency set at half the Nyquist frequency.} \label{compare-fir} \end{figure} +Fig. \ref{compare-fir} exhibits the +performance comparison between one solution and a monolithic FIR when selecting a cutoff +frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the +same space usage are provided as selected by the MILP solver. The FIR cascade provides improved +rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to +be tuned or compensated for. + + The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}. +We have considered a set of resources representative of the hardware platform we work on, +Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on +Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to +the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10 +filters fits in the available resources. However, in all cases the DSP resources are fully +used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software, +implementing the design fails due to the excessive resource usage preventing routing the signals +on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization +procedure by finding non-trivial solutions matching resource constraints, but on the other +hand also illustrates the limitation of a model with an abstraction layer that does not account +for the detailed architecture of the hardware. \begin{table}[h!tb] \caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade -- 2.16.4