From 0494f3f5bb86e11e71dc42f695b417e86c38a635 Mon Sep 17 00:00:00 2001 From: jmfriedt Date: Sun, 20 May 2018 19:49:37 +0200 Subject: [PATCH] corrections mineures --- ifcs2018_proceeding.tex | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/ifcs2018_proceeding.tex b/ifcs2018_proceeding.tex index 1ac70c3..4468e8e 100644 --- a/ifcs2018_proceeding.tex +++ b/ifcs2018_proceeding.tex @@ -1,3 +1,8 @@ +% JMF : revoir l'abstract : on y avait mis le Zynq7010 de la redpitaya en montrant +% comment optimiser les perfs a surface finie. Ici aussi on tombait dans le cas ou` +% la solution a 1 seul FIR n'etait simplement pas synthetisable => fusionner les deux +% contributions pour le papier TUFFC + \documentclass[a4paper,conference]{IEEEtran/IEEEtran} \usepackage{graphicx,color,hyperref} \usepackage{amsfonts} @@ -92,7 +97,7 @@ not only the coefficient values and number of taps must be defined, but also the defining the coefficients and the sample size. For this reason, and because we consider pipeline processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but -the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL). +the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level. Since latency is not an issue in a openloop phase noise characterization instrument, the large numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter, is not considered as an issue as would be in a closed loop system. @@ -199,13 +204,13 @@ Following these considerations, the model is expressed as: \begin{align} \begin{cases} \mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\ - \mathcal{A}_i &= N_i * C_i + D_i\\ + \mathcal{A}_i &= N_i \times (C_i + D_i)\\ \Delta_i &= \Delta _{i-1} + \mathcal{P}_i \end{cases} \label{model-FIR} \end{align} -To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$ -is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$. +To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the stopband rejection dependence with $N_i$ and $C_i$, $\mathcal{A}$ +is a theoretical area occupation of the processing block on the FPGA as discussed earlier, and $\Delta_i$ is the total rejection for the current stage $i$. Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements. @@ -224,13 +229,17 @@ rejection capability. Weighing these two criteria allows designing the linear pr \end{figure} The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below -a user-defined threshold. The MILP solver is allowed to choose the number of successive +a user-defined threshold, or aims at minimizing the area needed to reach a given rejection ($\min(S_q)$ in +the forthcoming discussion, Eqs. \ref{cstr_size} and \ref{cstr_rejection}). +The MILP solver is allowed to choose the number of successive filters, within an upper bound. The last problem is to model the noise rejection. Since filter noise rejection capability is not modeled with linear equations, a look-up-table is generated for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each -one of these conditions, the low-pass filter rejection defined as the mean power between -half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response -of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum +one of these conditions, the low-pass filter rejection is stored as computed by the frequency response +of the digital filter (Fig. \ref{noise-rejection}). Various rejection criteria have been investigated, +including mean value of the stopband response, median value of the stopband response, or as finally +selected, maximum value in the stopband. An intuitive analysis of the chart of Fig. \ref{noise-rejection} +hints at an optimum set of tap length and number of bit for representing the coefficients along the line of the pyramidal shaped rejection capability function. @@ -304,7 +313,7 @@ be tuned or compensated for. The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}. We have considered a set of resources representative of the hardware platform we work on, -Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on +Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results reported in Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10 filters fit in the available resources. However, in all cases the DSP resources are fully -- 2.16.4