Commit cac4c932ce7afb23be1594d0931c0e08f56af197

Authored by bmarechal
1 parent a52533e359
Exists in master

add rude gatetime setup

Showing 1 changed file with 19 additions and 9 deletions Side-by-side Diff

instruments/HP53132A.py
... ... @@ -37,22 +37,32 @@
37 37 self.configure()
38 38  
39 39 def configure(self):
40   - self.strCh = ''
41   - for ch in self.channels:
42   - self.send('%s (@%s)'%(CONF_VAL_TYPE[ALL_VAL_TYPE.index(self.vtypes[self.channels.index(ch)])], ch))
43   - self.strCh = self.strCh + '(@%s),'%ch
44   - self.strCh = self.strCh[0:-1]
45   - self.send('FORMAT ASCII')
  40 + #self.strCh = ''
  41 + #for ch in self.channels:
  42 + # self.send('%s (@%s)'%(CONF_VAL_TYPE[ALL_VAL_TYPE.index(self.vtypes[self.channels.index(ch)])], ch))
  43 + # self.strCh = self.strCh + '(@%s),'%ch
  44 + #self.strCh = self.strCh[0:-1]
  45 + #self.send('FORMAT ASCII')
46 46  
47 47 #self.send('ROUT:SCAN (@%s)'%self.strCh)
48 48 #self.send('TRIG:COUN 1')
49 49 self.send('*RST')
50   - self.send(":FUNC 'FREQ 1'")
51   - self.send(":ROSC:SOUR INT")
52   - self.send(":INIT:CONT ON")
  50 + #self.send('*CLS')
  51 + #self.send('*SRE 0')
  52 + #self.send('*ESE 0')
53 53  
  54 + self.send(':FUNC "FREQ 1"')
  55 + self.send(':FREQ:ARM:STAR:SOUR IMM')
  56 + self.send(':FREQ:ARM:STOP:SOUR TIM')
  57 + self.send(':FREQ:ARM:STOP:TIM 1')
  58 + self.send(':ROSC:SOUR EXT')
  59 + self.send(':ROSC:EXT:CHECK OFF')
  60 + #self.send(':STAT:PRES')
  61 + self.send(':INIT:CONT ON')
  62 +
54 63 def getValue(self):
55 64 self.send('FETC?')
  65 + #self.send('READ:FREQ?')
56 66 return self.read()
57 67  
58 68 def read(self):