From e3580faaed9916c30a80a4611d49775015d4a080 Mon Sep 17 00:00:00 2001 From: jmfriedt Date: Sun, 20 May 2018 08:28:56 +0200 Subject: [PATCH] relecture/corrections du matin --- ifcs2018_proceeding.tex | 206 +++++++++++++++++++----------------------------- 1 file changed, 83 insertions(+), 123 deletions(-) diff --git a/ifcs2018_proceeding.tex b/ifcs2018_proceeding.tex index d32acad..e004237 100644 --- a/ifcs2018_proceeding.tex +++ b/ifcs2018_proceeding.tex @@ -7,7 +7,6 @@ \usepackage{algorithm2e} \usepackage{url} \usepackage[normalem]{ulem} -\graphicspath{{/home/jmfriedt/gpr/170324_avalanche/}{/home/jmfriedt/gpr/1705_homemade/}} % correct bad hyphenation here \hyphenation{op-tical net-works semi-conduc-tor} \textheight=26cm @@ -91,7 +90,7 @@ As opposed to an implementation on a general purpose processor in which word siz processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since not only the coefficient values and number of taps must be defined, but also the number of bits defining the coefficients and the sample size. For this reason, and because we consider pipeline -processing (as opposed to First-In, First-Out memory batch processing) of radiofrequency +processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL). Since latency is not an issue in a openloop phase noise characterization instrument, the large @@ -117,6 +116,14 @@ will result in some precision loss. %\label{float_vs_int} %\end{figure} +\begin{figure}[h!tb] +\includegraphics[width=\linewidth]{images/demo_filtre} +\caption{Impact of the quantization resolution of the coefficients: the quantization is +set to 6~bits, setting the 30~first and 30~last coefficients out of the initial 128~band-pass +filter coefficients to 0.} +\label{float_vs_int} +\end{figure} + The tradeoff between quantization resolution and number of coefficients when considering integer operations is not trivial. As an illustration of the issue related to the relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits @@ -126,15 +133,14 @@ taps become null, making the large number of coefficients irrelevant and allowin processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources to reach a given rejection level, or maximizing out of band rejection for a given computational resource, will drive the investigation on cascading filters designed with varying tap resolution -and tap length, as will be shown in the next section. - -\begin{figure}[h!tb] -\includegraphics[width=\linewidth]{images/demo_filtre} -\caption{Impact of the quantization resolution of the coefficients: the quantization is -set to 6~bits, setting the 30~first and 30~last coefficients out of the initial 128~band-pass -filter coefficients to 0.} -\label{float_vs_int} -\end{figure} +and tap length, as will be shown in the next section. Indeed, our development strategy closely +follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards} +in which basic blocks are defined and characterized before being assembled \cite{hide} +in a complete processing chain. In our case, assembling the filter blocks is a simpler block +combination process since we assume a single value to be processed and a single value to be +generated at each clock cycle. The FIR filters will not be considered to decimate in the +current implementation: the decimation is assumed to be located after the FIR cascade at the +moment. \section{Filter optimization} @@ -163,13 +169,30 @@ the number of bits $C_i$ representing the coefficients and the number of bits $D the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage, the optimization of the complete processing chain within a constrained resource environment is not trivial. The resource occupation of a FIR filter is considered as $D_i+C_i \times N_i)$ which is -the number of bits needed in a worst case condition to represent the output of the FIR. -Unfortunately this representation is not sufficient to represent the real occupation inside FPGA. -In fact the FPGA have some BRAM block on which the coefficients are stored and each BRAM are not -share between different filters. Moreover the multiplication need DSP to be -perform. Those DSP are in limited quantity so in the future we shall to consider this. +the number of bits needed in a worst case condition to represent the output of the FIR. Such an +occupied area estimate assumes that the number of gates scales as the number of bits and the number +of coefficients, but does not account for the detailed implementation of the hardware. Indeed, +various FPGA implementations will provide different hardware functionalities, and we shall consider +at the end of the design a synthesis step using vendor software to assess the validity of the solution +found. As an example of the limitation linked to the lack of detailed hardware consideration, Block Random +Access Memory (BRAM) used to store filter coefficients are not shared amongst filters, and multiplications +are most efficiently implemented by using Digital Signal Processing (DSP) blocks whose input word +size is finite. DSPs are a scarce resource to be saved in a practical implementation. Keeping a high +abstraction on the resource occupation is nevertheless selected in the following discussion in order +to leave enough degrees of freedom in the problem to try and find original solutions: too many +constraints in the initial statement of the problem leave little room for finding an optimal solution. -At the moment our model can be express like this : +\begin{figure}[h!tb] +\begin{center} +\includegraphics[width=.5\linewidth]{schema2} +\caption{Shape of the filter: the bandpass BP is considered to occupy the initial +40\% of the Nyquist frequency range, the bandstop the last 40\%, allowing 20\% transition +width.} +\label{rejection-shape} +\end{center} +\end{figure} + +Following these considerations, the model is expressed as: \begin{align} \begin{cases} \mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\ @@ -178,20 +201,17 @@ At the moment our model can be express like this : \end{cases} \label{model-FIR} \end{align} -To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represent the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$ -is just theoretical occupation and $\Delta_i$ is the total rejection for the current stage $i$. At this moment -we are not able to express the function $\mathcal{F}$ so we are run some simulations to determine the rejection noise depending -on $N_i$ and $C_i$. But to choose the right filter we must define clearly the rejection criterion. If we take incorrect criterion -the linear program will produce a wrong solution. So we define a criterion to avoid ripple on passband and just keep -the maximum of rejection on the stopband (see the figure \ref{rejection-shape}). Thank to this system, we can able to design our linear program. - -\begin{figure}[h!tb] -\begin{center} -\includegraphics[width=.5\linewidth]{schema2} -\caption{Shape of rejection} -\label{rejection-shape} -\end{center} -\end{figure} +To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$ +is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$. +Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending +on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an +incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements. +Hence, amongst various criteria including the mean or median value of the FIR response in the stopband, we have designed +a criterion aimed at avoiding ripples on passband and considering the maximum of the FIR spectral response in the stopband +(Fig. \ref{rejection-shape}). The bandpass criterion is defined as the sum of the absolute values of the spectral response +in the bandpass, reminiscent of a standard deviation of the spectral response: this criterion must be minimized to avoid +ripples in the passband. The stopband transfer function maximum must also be minimized in order to improve the filter +rejection capability. Weighing these two criteria allows designing the linear program to be solved. \begin{figure}[h!tb] \includegraphics[width=\linewidth]{images/noise-rejection.pdf} @@ -202,7 +222,7 @@ the maximum of rejection on the stopband (see the figure \ref{rejection-shape}). The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below a user-defined threshold. The MILP solver is allowed to choose the number of successive filters, within an upper bound. The last problem is to model the noise rejection. Since filter -noise rejection capability is not modeled with linear equation, a look-up-table is generated +noise rejection capability is not modeled with linear equations, a look-up-table is generated for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each one of these conditions, the low-pass filter rejection defined as the mean power between half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response @@ -214,7 +234,7 @@ as linear equation and solved using one of the available solvers, in our case GL With the notation explain in system \ref{model-FIR}, we have defined our linear problem like this: \paragraph{Variables} \begin{align*} -x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a specific filter} \\ +x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a given filter} \\ & \text{ $j$ is the stage} \\ & \text{ If $x_{i,j}$ is equal to 1, the filter is selected} \\ \end{align*} @@ -222,24 +242,27 @@ x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a specific filter} \\ \begin{align*} \mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\ & \text{ $p$ is the number of different filters} \\ -C(i) & \text{ Constant to let the number of coefficients}\\ -& \text{ for the filter $i$}\\ -\pi_C(i) & \text{ Constant to let the number of bits of}\\ -& \text{ each coefficient for the filter $i$}\\ -\mathcal{A}_{\max} & \text{ Max space available inside the FPGA} +C(i) & \text{ % Constant to let the +number of coefficients %} \\ & \text{ +for filter $i$}\\ +\pi_C(i) & \text{ % Constant to let the +number of bits of %}\\ & \text{ +each coefficient for filter $i$}\\ +\mathcal{A}_{\max} & \text{ Total space available inside the FPGA} \end{align*} \paragraph{Constraints} -\begin{align*} -1 \leq i \leq p & \\ -1 \leq j \leq q & \text{ $q$ is the max of filter stage} \\ -\forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \\ -\mathcal{S}_0 = 0 & \text{ initial occupation}\\ -\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \forall i, x_{i,j} \times \mathcal{A}_i \\%\label{cstr_size} -\mathcal{S} \leq \mathcal{S}_{\max} \\ -\mathcal{N}_0 = 0 & \text{ initial rejection}\\ -\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \forall i, x_{i,j} \times \mathcal{R}_i \\%\label{cstr_rejection} -\mathcal{N}_q \geqslant 160 & \text{ an user's bound}\\ -\end{align*} +\begin{align} +1 \leq i \leq p & \nonumber\\ +1 \leq j \leq q & \text{ $q$ is the max of filter stage} \nonumber \\ +\forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \nonumber\\ +\mathcal{S}_0 = 0 & \text{ initial occupation} \nonumber\\ +\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \forall i, x_{i,j} \times \mathcal{A}_i \label{cstr_size} \\ +\mathcal{S} \leq \mathcal{S}_{\max}\nonumber \\ +\mathcal{N}_0 = 0 & \text{ initial rejection}\nonumber\\ +\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \forall i, x_{i,j} \times \mathcal{R}_i \label{cstr_rejection} \\ +\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\ +& \text{ (e.g. 160~dB here)}\nonumber\\\nonumber +\end{align} \paragraph{Goal} \begin{align*} \min \mathcal{S}_q @@ -293,12 +316,7 @@ FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline The coefficients of a single monolithic filter are computed as the impulse response of the filter transfer function, and practically approximated by a multitude of methods including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing -(Matlab's {\tt fir1} function). Cascading filters opens a new optimization opportunity by -selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2} -illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better -rejection than {\tt firls}: since the linear solver increases the number of coefficients along -the processing chain, the type of selected filter also changes depending on the number of coefficients -and evolves along the processing chain. +(Matlab's {\tt fir1} function). \begin{figure}[h!tb] \includegraphics[width=\linewidth]{images/fir1-vs-firls} @@ -308,6 +326,13 @@ encoded integers.} \label{2} \end{figure} +Cascading filters opens a new optimization opportunity by +selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2} +illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better +rejection than {\tt firls}: since the linear solver increases the number of coefficients along +the processing chain, the type of selected filter also changes depending on the number of coefficients +and evolves along the processing chain. + \section{Conclusion} We address the optimization problem of designing a low-pass filter chain in a Field Programmable Gate @@ -327,69 +352,9 @@ progress at the Time and Frequency Departments of the FEMTO-ST Institute The authors would like to thank E. Rubiola, F. Vernotte, G. Cabodevila for support and fruitful discussions. - -XXX - - \subsubsection{Contraintes} - - Dans les r\'ef\'erences \cite{zhuo2007scalable, olariu1993computing, pan1999improved}, les auteurs - proposent tous des optimisations hardware uniquement. Cependant ces articles sont focalis\'es sur des optimisations mat\'erielles - or notre objectif est de trouver une formalisation math\'ematique d'un FPGA. - - Une dernière approche que nous avons \'etudi\'ee est l'utilisation de \emph{skeletons}. D. Crookes et A. Benkrid - ont beaucoup parl\'e de cette m\'ethode dans leur articles \cite{crookes1998environment, crookes2000design, benkrid2002towards}. - L'id\'ee essentielle est qu'ils r\'ealisent des composants très optimis\'es et param\'etrables. Ainsi lorsqu'ils - veulent faire un d\'eveloppement, ils utilisent les blocs d\'ejà faits. - - Ces blocs repr\'esentent une \'etape de calcul (une d\'ecimation, un filtrage, une modulation, une - d\'emodulation etc...). En prenant le cas du FIR, on rend param\'etrables les valeurs des coefficients - utilis\'es pour le produit de convolutions ainsi que leur nombre. Le facteur de d\'ecimation est - lui aussi param\'etrable. - - On gagne ainsi beaucoup de temps de d\'eveloppement car on r\'eutilise des composants d\'ejà \'eprouv\'es et optimis\'es. - De plus, au fil des projets, on constitue une bibliothèque de composants nous - permettant de faire une chaine complète très simplement. - - K. Benkrid, S. Belkacemi et A. Benkrid dans leur article\cite{hide} caract\'erisent - ces blocs en Prolog pour faire un langage descriptif permettant d'assembler les blocs de manière - optimale. En partant de cette description, ils arrivent à g\'en\'erer directement le code VHDL. - - \begin{itemize} - \item la latence du bloc repr\'esente, en coups d'horloge, le temps entre l'entr\'ee de la donn\'ee - et le temps où la même donn\'ee ressort du bloc. - \item l'acceptance repr\'esente le nombre de donn\'ees par coup d'horloge que le bloc est capable - de traiter. - \item la sortance repr\'esente le nombre de donn\'ees qui sortent par coup d'horloge. - \end{itemize} - - Gr\^ace à cela, le logiciel est capable de donner une impl\'ementation optimale d'un problème qu'on lui - soumet. Le problème ne se d\'efinit pas uniquement par un r\'esultat attendu mais aussi par des - contraintes de d\'ebit et/ou de pr\'ecision. - - Dans une second temps, nous nous sommes aussi int\'eress\'es à des articles d'ordonnancement. - Nous avons notamment lu des documents parlant des cas des micro-usines. - - Les micro-usines ressemblent un peu à des FPGA dans le sens où on connait à l'avance les - t\^aches à effectuer et leurs caract\'eristiques. Nous allons donc nous inspirer - de leur modèle pour essayer de construire le notre. - - Dans sa thèse A. Dobrila \cite{these-alex} traite d'un problème de tol\'erance aux pannes - dans le contextes des mirco-usines. Mais les FPGA ne sont pas concern\'es dans la mesure - où si le composant tombe en panne, tout le traitement est paralys\'e. Cette thèse nous a n\'eanmoins - permis d'avoir un exemple de formalisation de problème. - - Pour finir nous avons lu la thèse de M. Coqblin \cite{these-mathias} qui elle aussi traite du sujet - des micro-usines. Le travail de M. Coqblin porte surtout sur une chaine de traitement - reconfigurable, il tient compte dans ses travaux du surcoût engendr\'e par la reconfiguration d'une machine. - Cela n'est pas tout à fait exploitable dans notre contexte puisqu'une - puce FPGA d\'es qu'elle est programm\'ee n'a pas la possibilit\'e de reconfigurer une partie de sa chaine de - traitement. Là encore, nous avions un exemple de formalisation d'un problème. - - Pour conclure, nous avons vu deux approches li\'ees à deux domaines diff\'erents. La première est le - point de vue \'electronique qui se focalise principalement sur des optimisations mat\'erielles ou algorithmiques. - La seconde est le point de vue informatique : les modèles sont très g\'en\'eriques et ne sont pas - adapt\'es au cas des FPGA. La suite de ce rapport se concentrera donc sur la recherche d'un compromis - entre ces deux points de vue. +\bibliographystyle{IEEEtran} +\bibliography{references,biblio} +\end{document} \section{Contexte d'ordonnancement} Dans cette partie, nous donnerons des d\'efinitions de termes rattach\'es au domaine de l'ordonnancement @@ -461,7 +426,6 @@ XXX des critères peut être très mauvaise pour un autre critère. De ce cas, il s'agira de trouver une solution qui permet de faire le meilleur compromis entre tous les critères. - \subsection{Formalisation du problème} \label{formalisation} Maintenant que nous avons donn\'e le vocabulaire li\'e à l'ordonnancement, nous allons pouvoir essayer caract\'eriser @@ -619,7 +583,3 @@ XXX Bien que les articles sur les skeletons, \cite{gwen-cogen}, \cite{skeleton} et \cite{hide}, nous aient donn\'e des indices sur une possible mod\'elisation, ils \'etaient encore trop focalis\'es sur l'optimisation spatiale des blocs. Nous nous sommes donc inspir\'es de ces travaux pour proposer notre modèle, en faisant abstraction des optimisations bas niveau. - -\bibliographystyle{IEEEtran} -\bibliography{references,biblio} -\end{document} -- 2.16.4