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% fusionner max rejection a surface donnee v.s minimiser surface a rejection donnee 1 File was deleted
% demontrer comment la quantification rejette du bruit vers les hautes frequences => 6 dB de 2
% rejection par bit et perte si moins de bits que rejection/6 3
% developper programme lineaire en incluant le decalage de bits 4
% insister que avant on etait synthetisable mais pas implementable, alors que maintenant on 5
% implemente et on demontre que ca tourne 6
% gwen : pourquoi le FIR est desormais implementable et ne l'etait pas meme sur zedboard->new FIR ? 7
% Gwen : peut-on faire un vrai banc de bruit de phase avec ce FIR, ie ajouter ADC, NCO et mixer 8
% (zedboard ou redpit) 9
10
\documentclass[a4paper,transaction]{IEEEtran/IEEEtran} 11
\usepackage{graphicx,color,hyperref} 12
\usepackage{amsfonts} 13
\usepackage{amsthm} 14
\usepackage{amssymb} 15
\usepackage{amsmath} 16
\usepackage{algorithm2e} 17
\usepackage{url,balance} 18
\usepackage[normalem]{ulem} 19
% correct bad hyphenation here 20
\hyphenation{op-tical net-works semi-conduc-tor} 21
\textheight=26cm 22
\setlength{\footskip}{30pt} 23
\pagenumbering{gobble} 24
\begin{document} 25
\title{Filter optimization for real time digital processing of radiofrequency signals: application 26
to oscillator metrology} 27
28
\author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2}, 29
G. Goavec-M\'erou\IEEEauthorrefmark{1}, 30
P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}} 31
\IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France } 32
\IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\ 33
Email: \{pyb2,jmfriedt\}@femto-st.fr} 34
} 35
\maketitle 36
\thispagestyle{plain} 37
\pagestyle{plain} 38
\newtheorem{definition}{Definition} 39
40
\begin{abstract} 41
Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to 42
radiofrequency signal processing. Applied to oscillator characterization in the context 43
of ultrastable clocks, stringent filtering requirements are defined by spurious signal or 44
noise rejection needs. Since real time radiofrequency processing must be performed in a 45
Field Programmable Array to meet timing constraints, we investigate optimization strategies 46
to design filters meeting rejection characteristics while limiting the hardware resources 47
required and keeping timing constraints within the targeted measurement bandwidths. 48
\end{abstract} 49
50
\begin{IEEEkeywords} 51
Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter 52
\end{IEEEkeywords} 53
54
\section{Digital signal processing of ultrastable clock signals} 55
56
Analog oscillator phase noise characteristics are classically performed by downconverting 57
the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband, 58
followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In 59
a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by 60
multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}. 61
62
\begin{figure}[h!tb] 63
\begin{center} 64
\includegraphics[width=.8\linewidth]{schema} 65
\end{center} 66
\caption{Fully digital oscillator phase noise characterization: the Device Under Test 67
(DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and 68
downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals 69
and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite 70
Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays 71
the spectral characteristics of the phase fluctuations.} 72
% JMF : argumenter de la cascade de FIR 73
\label{schema} 74
\end{figure} 75
76
As with the analog mixer, 77
the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as 78
well as the generation of the frequency sum signal in addition to the frequency difference. 79
These unwanted spectral characteristics must be rejected before decimating the data stream 80
for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the 81
downconverter 82
and the decimation processing blocks are core characteristics of an oscillator characterization 83
system, and must reject out-of-band signals below the targeted phase noise -- typically in the 84
sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will 85
use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency 86
datastream: optimizing the performance of the filter while reducing the needed resources is 87
hence tackled in a systematic approach using optimization techniques. Most significantly, we 88
tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with 89
tunable number of coefficients and tunable number of bits representing the coefficients and the 90
data being processed. 91
92
\section{Finite impulse response filter} 93
94
We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined 95
by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the 96
outputs $y_k$ 97
$$y_n=\sum_{k=0}^N b_k x_{n-k}$$ 98
99
As opposed to an implementation on a general purpose processor in which word size is defined by the 100
processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since 101
not only the coefficient values and number of taps must be defined, but also the number of bits 102
defining the coefficients and the sample size. For this reason, and because we consider pipeline 103
processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency 104
signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but 105
the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level. 106
Since latency is not an issue in a openloop phase noise characterization instrument, the large 107
numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter, 108
is not considered as an issue as would be in a closed loop system. 109
110
The coefficients are classically expressed as floating point values. However, this binary 111
number representation is not efficient for fast arithmetic computation by an FPGA. Instead, 112
we select to quantify these floating point values into integer values. This quantization 113
will result in some precision loss. 114
115
%As illustrated in Fig. \ref{float_vs_int}, we see that we aren't 116
%need too coefficients or too sample size. If we have lot of coefficients but a small sample size, 117
%the first and last are equal to zero. But if we have too sample size for few coefficients that not improve the quality. 118
119
% JMF je ne comprends pas la derniere phrase ci-dessus ni la figure ci dessous 120
% AH en gros je voulais dire que prendre trop peu de bit avec trop de coeff, ça induit ta figure (bien mieux faite que moi) 121
% et que l'inverse trop de bit sur pas assez de coeff on ne gagne rien, je vais essayer de la reformuler 122
123
%\begin{figure}[h!tb] 124
%\includegraphics[width=\linewidth]{images/float-vs-integer.pdf} 125
%\caption{Impact of the quantization resolution of the coefficients} 126
%\label{float_vs_int} 127
%\end{figure} 128
129
\begin{figure}[h!tb] 130
\includegraphics[width=\linewidth]{images/demo_filtre} 131
\caption{Impact of the quantization resolution of the coefficients: the quantization is 132
set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting 133
the 30~first and 30~last coefficients out of the initial 128~band-pass 134
filter coefficients to 0 (red dots).} 135
\label{float_vs_int} 136
\end{figure} 137
138
The tradeoff between quantization resolution and number of coefficients when considering 139
integer operations is not trivial. As an illustration of the issue related to the 140
relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits 141
a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon 142
quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the 143
taps become null, making the large number of coefficients irrelevant and allowing to save 144
processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources 145
to reach a given rejection level, or maximizing out of band rejection for a given computational 146
resource, will drive the investigation on cascading filters designed with varying tap resolution 147
and tap length, as will be shown in the next section. Indeed, our development strategy closely 148
follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards} 149
in which basic blocks are defined and characterized before being assembled \cite{hide} 150
in a complete processing chain. In our case, assembling the filter blocks is a simpler block 151
combination process since we assume a single value to be processed and a single value to be 152
generated at each clock cycle. The FIR filters will not be considered to decimate in the 153
current implementation: the decimation is assumed to be located after the FIR cascade at the 154
moment. 155
156
\section{Filter optimization} 157
158
A basic approach for implementing the FIR filter is to compute the transfer function of 159
a monolithic filter: this single filter defines all coefficients with the same resolution 160
(number of bits) and processes data represented with their own resolution. Meeting the 161
filter shape requires a large number of coefficients, limited by resources of the FPGA since 162
this filter must process data stream at the radiofrequency sampling rate after the mixer. 163
164
An optimization problem \cite{leung2004handbook} aims at improving one or many 165
performance criteria within a constrained resource environment. Amongst the tools 166
developed to meet this aim, Mixed-Integer Linear Programming (MILP) provides the framework to 167
formally define the stated problem and search for an optimal use of available 168
resources \cite{yu2007design, kodek1980design}. 169
170
First we need to ensure that our problem is a real optimization problem. When 171
designing a processing function in the FPGA, we aim at meeting some requirement such as 172
the throughput, the computation time or the noise rejection noise. However, due to limited 173
resources to design the process like BRAM (high performance RAM), DSP (Digital Signal Processor) 174
or LUT (Look Up Table), a tradeoff must be generally searched between performance and available 175
computational resources: optimizing some criteria within finite, limited 176
resources indeed matches the definition of a classical optimization problem. 177
178
Specifically the degrees of freedom when addressing the problem of replacing the single monolithic 179
FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$, 180
the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ needed to represent 181
the data $x_k$ fed to each filter as provided by the acquisition or previous processing stage. 182
Because each FIR in the chain is fed the output of the previous stage, 183
the optimization of the complete processing chain within a constrained resource environment is not 184
trivial. The resource occupation of a FIR filter is considered as $C_i \times N_i$ which aims 185
at approximating the number of bits needed in a worst case condition to represent the output of the 186
FIR. Indeed, the number of bits generated by the $i$th FIR is $(C_i+D_i)\times\log_2(N_i)$, but the 187
$\log$ function is avoided for its incompatibility with a linear programming description, and 188
the simple product is approximated as the number of gates needed to perform the calculation. Such an 189
occupied area estimate assumes that the number of gates scales as the number of bits and the number 190
of coefficients, but does not account for the detailed implementation of the hardware. Indeed, 191
various FPGA implementations will provide different hardware functionalities, and we shall consider 192
at the end of the design a synthesis step using vendor software to assess the validity of the solution 193
found. As an example of the limitation linked to the lack of detailed hardware consideration, Block Random 194
Access Memory (BRAM) used to store filter coefficients are not shared amongst filters, and multiplications 195
are most efficiently implemented by using DSP blocks whose input word 196
size is finite. DSPs are a scarce resource to be saved in a practical implementation. Keeping a high 197
abstraction on the resource occupation is nevertheless selected in the following discussion in order 198
to leave enough degrees of freedom in the problem to try and find original solutions: too many 199
constraints in the initial statement of the problem leave little room for finding an optimal solution. 200
201
\begin{figure}[h!tb] 202
\begin{center} 203
\includegraphics[width=.5\linewidth]{schema2} 204
\caption{Shape of the filter transmitted power $P$ as a function of frequency: 205
the bandpass BP is considered to occupy the initial 206
40\% of the Nyquist frequency range, the stopband the last 40\%, allowing 20\% transition 207
width.} 208
\label{rejection-shape} 209
\end{center} 210
\end{figure} 211
212
Following these considerations, the model is expressed as: 213
\begin{align} 214
\begin{cases} 215
\mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\ 216
\mathcal{A}_i &= N_i \times C_i\\ 217
\Delta_i &= \Delta _{i-1} + \mathcal{P}_i 218
\end{cases} 219
\label{model-FIR} 220
\end{align} 221
To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the stopband rejection dependence with $N_i$ and $C_i$, $\mathcal{A}_i$ 222
is a theoretical area occupation of the processing block on the FPGA as discussed earlier, and $\Delta_i$ is the total rejection for the current stage $i$. 223
Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending 224
on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an 225
incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements. 226
Hence, amongst various criteria including the mean or median value of the FIR response in the stopband as will 227
be illustrated lated (section \ref{median}), we have designed 228
a criterion aimed at avoiding ripples in the passband and considering the maximum of the FIR spectral response in the stopband 229
(Fig. \ref{rejection-shape}). The bandpass criterion is defined as the sum of the absolute values of the spectral response 230
in the bandpass, reminiscent of a standard deviation of the spectral response: this criterion must be minimized to avoid 231
ripples in the passband. The stopband transfer function maximum must also be minimized in order to improve the filter 232
rejection capability. Weighing these two criteria allows designing the linear program to be solved. 233
234
\begin{figure}[h!tb] 235
\includegraphics[width=\linewidth]{images/noise-rejection.pdf} 236
\caption{Rejection as a function of number of coefficients and number of bits.} 237
\label{noise-rejection} 238
\end{figure} 239
240
{\bf ARTHUR : reg\'en\'erer une pyramide juste} 241
242
The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource 243
occupation below a user-defined threshold, or as will be discussed here, aims at minimizing the area 244
needed to reach a given rejection ($\min(S_q)$ in the forthcoming discussion, Eqs. \ref{cstr_size} 245
and \ref{cstr_rejection}). The MILP solver is allowed to choose the number of successive 246
filters, within an upper bound. The last problem is to model the noise rejection. Since filter 247
noise rejection capability is not modeled with linear equations, a look-up-table is generated 248
for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each 249
one of these conditions, the low-pass filter rejection is stored as computed by the frequency response 250
of the digital filter (Fig. \ref{noise-rejection}). Various rejection criteria have been investigated, 251
including mean value of the stopband response, median value of the stopband response, or as finally 252
selected, maximum value in the stopband. An intuitive analysis of the chart of Fig. \ref{noise-rejection} 253
hints at an optimum 254
set of tap length and number of bit for representing the coefficients along the line of the pyramidal 255
shaped rejection capability function. 256
257
Linear program formalism for solving the problem is well documented: an objective function is 258
defined which is linearly dependent on the parameters to be optimized. Constraints are expressed 259
as linear equations and solved using one of the available solvers, in our case GLPK\cite{glpk}. 260
With the notations used in the description of system \ref{model-FIR}, we have defined the linear problem as: 261
\paragraph{Variables} 262
\begin{align*} 263
x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a given filter} \\ 264
& \text{ $j$ is the stage} \\ 265
& \text{ If $x_{i,j}$ is equal to 1, the filter is selected} \\ 266
\end{align*} 267
\paragraph{Constants} 268
\begin{align*} 269
\mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\ 270
& \text{ $p$ is the number of different filters} \\ 271
% N(i) & \text{ % Constant to let the 272
% number of coefficients %} \\ & \text{ 273
% for filter $i$}\\ 274
% C(i) & \text{ % Constant to let the 275
% number of bits of %}\\ & \text{ 276
% each coefficient for filter $i$}\\ 277
\mathcal{S}_{\max} & \text{ Total space available inside the FPGA} 278
\end{align*} 279
\paragraph{Constraints} 280
\begin{align} 281
1 \leq i \leq p & \nonumber\\ 282
1 \leq j \leq q & \text{ $q$ is the max of filter stage} \nonumber \\ 283
\forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \nonumber\\ 284
\mathcal{S}_0 = 0 & \text{ initial occupation} \nonumber\\ 285
\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{A}_i)} \label{cstr_size} \\ 286
\mathcal{S}_j \leq \mathcal{S}_{\max}\nonumber \\ 287
\mathcal{N}_0 = 0 & \text{ initial rejection}\nonumber\\ 288
\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{R}_i)} \label{cstr_rejection} \\ 289
\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\ 290
& \text{ (e.g. 160~dB here)}\nonumber\\\nonumber 291
\end{align} 292
\paragraph{Goal} 293
\begin{align*} 294
\min \mathcal{S}_q 295
\end{align*} 296
297
The constraint \ref{cstr_size} means the occupation for the current stage $j$ depends on 298
the previous occupation and the occupation of current selected filter (it is possible 299
that no filter is selected for this stage). And the second one \ref{cstr_rejection} 300
means the same thing but for the rejection, the rejection depends the previous rejection 301
plus the rejection of selected filter. 302
303
\subsection{Low bandpass ripple and maximum rejection criteria} 304
305
The MILP solver provides a solution to the problem by selecting a series of small FIR with 306
increasing number of bits representing data and coefficients as well as an increasing number 307
of coefficients, instead of a single monolithic filter. 308
309
\begin{figure}[h!tb] 310
% \includegraphics[width=\linewidth]{images/compare-fir.pdf} 311
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-jmf-light.pdf} 312
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 313
with a cutoff frequency set at half the Nyquist frequency.} 314
\label{compare-fir} 315
\end{figure} 316
317
Fig. \ref{compare-fir} exhibits the 318
performance comparison between one solution and a monolithic FIR when selecting a cutoff 319
frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the 320
same space usage are provided as selected by the MILP solver. The FIR cascade provides improved 321
rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to 322
be tuned or compensated for. 323
324
325
The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}. 326
We have considered a set of resources representative of the hardware platform we work on, 327
Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results reported in 328
Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to 329
the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10 330
filters fit in the available resources. However, in all cases the DSP resources are fully 331
used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software, 332
implementing the design fails due to the excessive resource usage preventing routing the signals 333
on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization 334
procedure by finding non-trivial solutions matching resource constraints, but on the other 335
hand also illustrates the limitation of a model with an abstraction layer that does not account 336
for the detailed architecture of the hardware. 337
338
\begin{table}[h!tb] 339
\caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade 340
identified as optimal by the MILP solver within a finite resource criterion. The last line refers 341
to available resources on a Zynq-7020 as found on the Zedboard.} 342
\begin{center} 343
\begin{tabular}{|c|cccc|}\hline 344
FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline 345
1 (monolithic) & 1 & 76183 & 220 & -162 \\ 346
5 & 5 & 18597 & 220 & -160 \\ 347
10 & 8 & 24729 & 220 & -161 \\\hline\hline 348
\textbf{Zynq 7020} & \textbf{420} & \textbf{53200} & \textbf{220} & \\\hline 349
%\begin{tabular}{|c|ccccc|}\hline 350
%FIR & BRAM36 & BRAM18 & LUT & DSP & rejection (dB)\\\hline\hline 351
%1 (monolithic) & 1 & 0 & {\color{Red}76183} & 220 & -162 \\ 352
%5 & 0 & 5 & {\color{Green}18597} & 220 & -160 \\ 353
%10 & 0 & 8 & {\color{Green}24729} & 220 & -161 \\\hline\hline 354
%\textbf{Zynq 7020} & \textbf{140} & \textbf{280} & \textbf{53200} & \textbf{220} & \\\hline 355
\end{tabular} 356
\end{center} 357
%\vspace{-0.7cm} 358
\label{t1} 359
\end{table} 360
361
\subsection{Alternate criteria}\label{median} 362
363
Fig. \ref{compare-fir} provides FIR solutions matching well the targeted transfer 364
function, namely low ripple in the bandpass defined as the first 40\% of the frequency 365
range and maximum rejection of 160~dB in the last 40\% stopband. We illustrate now, for 366
demonstrating the need to properly select the optimization criterion, two cases of poor 367
filter shapes obtained by selecting the mean value and median value of the rejection, 368
with no consideration for the ripples in the bandpass. The results of the optimizations, 369
in these cases, are shown in Figs. \ref{compare-mean} and \ref{compare-median}. 370
371
\begin{figure}[h!tb] 372
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-mean-light.pdf} 373
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 374
with a cutoff frequency set at half the Nyquist frequency.} 375
\label{compare-mean} 376
\end{figure} 377
378
In the case of the mean value criterion (Fig. \ref{compare-mean}), the solution is not 379
acceptable since the notch at the end of the transition band compensates for some unacceptable 380
rise in the rejection close to the Nyquist frequency. Applying such a filter might yield excessive 381
high frequency spurious components to be aliased at low frequency when decimating the signal. 382
Similarly, the lack of criterion on the bandpass shape induces a shape with poor flatness and 383
and slowly decaying transfer function starting to attenuate spectral components well before the 384
transition band starts. Such issues are partly aleviated by replacing a mean rejection value with 385
a median rejection value (Fig. \ref{compare-median}) but solutions remain unacceptable for 386
the reasons stated previously and much poorer than those found with the maximum rejection criterion 387
selected earlier (Fig. \ref{compare-fir}). 388
389
\begin{figure}[h!tb] 390
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-median-light.pdf} 391
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 392
with a cutoff frequency set at half the Nyquist frequency.} 393
\label{compare-median} 394
\end{figure} 395
396
\section{Filter coefficient selection} 397
398
The coefficients of a single monolithic filter are computed as the impulse response 399
of the filter transfer function, and practically approximated by a multitude of methods 400
including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing 401
(Matlab's {\tt fir1} function). 402
403
\begin{figure}[h!tb] 404
\includegraphics[width=\linewidth]{images/fir1-vs-firls} 405
\caption{Evolution of the rejection capability of least-square optimized filters and Hamming 406
FIR filters as a function of the number of coefficients, for floating point numbers and 8-bit 407
encoded integers.} 408
\label{2} 409
\end{figure} 410
411
Cascading filters opens a new optimization opportunity by 412
selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2} 413
illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better 414
rejection than {\tt firls}: since the linear solver increases the number of coefficients along 415
the processing chain, the type of selected filter also changes depending on the number of coefficients 416
and evolves along the processing chain. 417
418
\section{Conclusion} 419
420
We address the optimization problem of designing a low-pass filter chain in a Field Programmable Gate 421
Array for improved noise rejection within constrained resource occupation, as needed for 422
real time processing of radiofrequency signal when characterizing spectral phase noise 423
characteristics of stable oscillators. The flexibility of the digital approach makes the result 424
best suited for closing the loop and using the measurement output in a feedback loop for 425
controlling clocks, e.g. in a quartz-stabilized high performance clock whose long term behavior 426
is controlled by non-piezoelectric resonator (sapphire resonator, microwave or optical 427
atomic transition). 428
429
\section*{Acknowledgement} 430
431
This work is supported by the ANR Programme d'Investissement d'Avenir in 432
progress at the Time and Frequency Departments of the FEMTO-ST Institute 433
(Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e. 434
The authors would like to thank E. Rubiola, F. Vernotte, and G. Cabodevila 435
for support and fruitful discussions. 436
437
\bibliographystyle{IEEEtran} 438
\balance 439
\bibliography{references,biblio} 440
\end{document} 441
442
\section{Contexte d'ordonnancement} 443
Dans cette partie, nous donnerons des d\'efinitions de termes rattach\'es au domaine de l'ordonnancement 444
et nous verrons que le sujet trait\'e se rapproche beaucoup d'un problème d'ordonnancement. De ce fait 445
nous pourrons aller plus loin que les travaux vus pr\'ec\'edemment et nous tenterons des approches d'ordonnancement 446
et d'optimisation. 447
448
\subsection{D\'efinition du vocabulaire} 449
Avant tout, il faut d\'efinir ce qu'est un problème d'optimisation. Il y a deux d\'efinitions 450
importantes à donner. La première est propos\'ee par Legrand et Robert dans leur livre \cite{def1-ordo} : 451
\begin{definition} 452
\label{def-ordo1} 453
Un ordonnancement d'un système de t\^aches $G\ =\ (V,\ E,\ w)$ est une fonction $\sigma$ : 454
$V \rightarrow \mathbb{N}$ telle que $\sigma(u) + w(u) \leq \sigma(v)$ pour toute arête $(u,\ v) \in E$. 455
\end{definition} 456
457
Dit plus simplement, l'ensemble $V$ repr\'esente les t\^aches à ex\'ecuter, l'ensemble $E$ repr\'esente les d\'ependances 458
des t\^aches et $w$ les temps d'ex\'ecution de la t\^ache. La fonction $\sigma$ donne donc l'heure de d\'ebut de 459
chacune des t\^aches. La d\'efinition dit que si une t\^ache $v$ d\'epend d'une t\^ache $u$ alors 460
la date de d\'ebut de $v$ sera plus grande ou \'egale au d\'ebut de l'ex\'ecution de la t\^ache $u$ plus son 461
temps d'ex\'ecution. 462
463
Une autre d\'efinition importante qui est propos\'ee par Leung et al. \cite{def2-ordo} est : 464
\begin{definition} 465
\label{def-ordo2} 466
L'ordonnancement traite de l'allocation de ressources rares à des activit\'es avec 467
l'objectif d'optimiser un ou plusieurs critères de performance. 468
\end{definition} 469
470
Cette d\'efinition est plus g\'en\'erique mais elle nous int\'eresse d'avantage que la d\'efinition \ref{def-ordo1}. 471
En effet, la partie qui nous int\'eresse dans cette première d\'efinition est le respect de la pr\'ec\'edance des t\^aches. 472
Dans les faits les dates de d\'ebut ne nous int\'eressent pas r\'eellement. 473
474
En revanche la d\'efinition \ref{def-ordo2} sera au c\oe{}ur du projet. Pour se convaincre de cela, 475
il nous faut d'abord d\'efinir quel est le type de problème d'ordonnancement qu'on traite et quelles 476
sont les m\'ethodes qu'on peut appliquer. 477
478
Les problèmes d'ordonnancement peuvent être class\'es en diff\'erentes cat\'egories : 479
\begin{itemize} 480
\item T\^aches ind\'ependantes : dans cette cat\'egorie de problèmes, les t\^aches sont complètement ind\'ependantes 481
les unes des autres. Dans notre cas, ce n'est pas le plus adapt\'e. 482
\item Graphe de t\^aches : la d\'efinition \ref{def-ordo1} d\'ecrit cette cat\'egorie. La plupart du temps, 483
les t\^aches sont repr\'esent\'ees par une DAG. Cette cat\'egorie est très proche de notre cas puisque nous devons \'egalement ex\'ecuter 484
des t\^aches qui ont un certain nombre de d\'ependances. On pourra même dire que dans certain cas, 485
on a des anti-arbres, c'est à dire que nous avons une multitude de t\^aches d'entr\'ees qui convergent vers une 486
t\^ache de fin. 487
\item Workflow : cette cat\'egorie est une sous cat\'egorie des graphes de t\^aches dans le sens où 488
il s'agit d'un graphe de t\^aches r\'ep\'et\'e de nombreuses de fois. C'est exactement ce type de problème 489
que nous traitons ici. 490
\end{itemize} 491
492
Bien entendu, cette liste n'est pas exhaustive et il existe de nombreuses autres classifications et sous-classifications 493
de ces problèmes. Nous n'avons parl\'e ici que des cat\'egories les plus communes. 494
495
Un autre point à d\'efinir, est le critère d'optimisation. Il y a là encore un grand nombre de 496
critères possibles. Nous allons donc parler des principaux : 497
\begin{itemize} 498
\item Temps de compl\'etion total (ou Makespan en anglais) : ce critère est l'un des critères d'optimisation 499
les plus courant. Il s'agit donc de minimiser la date de fin de la dernière t\^ache de l'ensemble des 500
t\^aches à ex\'ecuter. L'enjeu de cette optimisation est donc de trouver l'ordonnancement optimal permettant 501
la fin d'ex\'ecution au plus tôt. 502
\item Somme des temps d'ex\'ecution (Flowtime en anglais) : il s'agit de faire la somme des temps d'ex\'ecution de toutes les t\^aches 503
et d'optimiser ce r\'esultat. 504
\item Le d\'ebit : ce critère quant à lui, vise à augmenter au maximum le d\'ebit de traitement des donn\'ees. 505
\end{itemize} 506
507
En plus de cela, on peut avoir besoin de plusieurs critères d'optimisation. Il s'agit dans ce cas d'une optimisation 508
multi-critères. Bien entendu, cela complexifie d'autant plus le problème car la solution la plus optimale pour un 509
des critères peut être très mauvaise pour un autre critère. De ce cas, il s'agira de trouver une solution qui permet 510
de faire le meilleur compromis entre tous les critères. 511
512
\subsection{Formalisation du problème} 513
\label{formalisation} 514
Maintenant que nous avons donn\'e le vocabulaire li\'e à l'ordonnancement, nous allons pouvoir essayer caract\'eriser 515
formellement notre problème. En effet, nous allons reprendre les contraintes \'enonc\'ees dans la sections \ref{def-contraintes} 516
et nous essayerons de les formaliser le plus finement possible. 517
518
Comme nous l'avons dit, une t\^ache est un bloc de traitement. Chaque t\^ache $i$ dispose d'un ensemble de paramètres 519
que nous nommerons $\mathcal{P}_{i}$. Cet ensemble $\mathcal{P}_i$ est propre à chaque t\^ache et il variera d'une 520
t\^ache à l'autre. Nous reviendrons plus tard sur les paramètres qui peuvent composer cet ensemble. 521
522
Outre cet ensemble $\mathcal{P}_i$, chaque t\^ache dispose de paramètres communs : 523
\begin{itemize} 524
\item Dur\'ee de la t\^ache : Comme nous l'avons dit auparavant, dans le cadre d'un FPGA le temps est compt\'e en nombre de coup d'horloge. 525
En outre, les blocs sont toujours sollicit\'es, certains même sont capables de lire et de renvoyer une r\'esultat à chaque coups d'horloge. 526
Donc la dur\'ee d'une t\^ache ne peut être le laps de temps entre l'entr\'ee d'une donn\'ee et la sortie d'une autre. Nous d\'efinirons la 527
dur\'ee comme le temps de traitement d'une donn\'ee, c'est à dire la diff\'erence de temps entre la date de sortie d'une donn\'ee 528
et de sa date d'entr\'ee. Nous nommerons cette dur\'ee $\delta_i$. % Je devrais la nomm\'ee w comme dans la def2 529
\item La pr\'ecision : La pr\'ecision d'une donn\'ee est le nombre de bits significatifs qu'elle compte. En effet, au fil des traitements 530
les pr\'ecisions peuvent varier. On nomme donc la pr\'ecision d'entr\'ee d'une t\^ache $i$ comme $\pi_i^-$ et la pr\'ecision en sortie $\pi_i^+$. 531
\item La fr\'equence du flux en entr\'ee (ou sortie) : Cette fr\'equence repr\'esente la fr\'equence des donn\'ees qui arrivent (resp. sortent). 532
Selon les t\^aches, les fr\'equences varieront. En effet, certains blocs ralentissent le flux c'est pourquoi on distingue la fr\'equence du 533
flux en entr\'ee et la fr\'equence en sortie. Nous nommerons donc la fr\'equence du flux en entr\'ee $f_i^-$ et la fr\'equence en sortie $f_i^+$. 534
\item La quantit\'e de donn\'ees en entr\'ee (ou en sortie) : Il s'agit de la quantit\'e de donn\'ees que le bloc s'attend à traiter (resp. 535
est capable de produire). Les t\^aches peuvent avoir à traiter des gros volumes de donn\'ees et n'en ressortir qu'une partie. Cette 536
fois encore, il nous faut donc diff\'erencier l'entr\'ee et la sortie. Nous nommerons donc la quantit\'e de donn\'ees entrantes $q_i^-$ 537
et la quantit\'e de donn\'ees sortantes $q_i^+$ pour une t\^ache $i$. 538
\item Le d\'ebit d'entr\'ee (ou de sortie) : Ce paramètre correspond au d\'ebit de donn\'ees que la t\^ache est capable de traiter ou qu'elle 539
fournit en sortie. Il s'agit simplement de l'expression des deux pr\'ec\'edents paramètres. Nous d\'efinirons donc la d\'ebit entrant de la 540
t\^ache $i$ comme $d_i^-\ =\ q_i^-\ *\ f_i^-$ et le d\'ebit sortant comme $d_i^+\ =\ q_i^+\ *\ f_i^+$. 541
\item La taille de la t\^ache : La taille dans les FPGA \'etant limit\'ee, ce paramètre exprime donc la place qu'occupe la t\^ache au sein du bloc. 542
Nous nommerons $\mathcal{A}_i$ cette taille. 543
\item Les pr\'ed\'ecesseurs et successeurs d'une t\^ache : cela nous permet de connaître les t\^aches requises pour pouvoir traiter 544
la t\^ache $i$ ainsi que les t\^aches qui en d\'ependent. Ces ensemble sont not\'es $\Gamma _i ^-$ et $ \Gamma _i ^+$ \\ 545
%TODO Est-ce vraiment un paramètre ? 546
\end{itemize} 547
548
Ces diff\'erents paramètres communs sont fortement li\'es aux \'el\'ements de $\mathcal{P}_i$. Voici quelques exemples de relations 549
que nous avons identifi\'ees : 550
\begin{itemize} 551
\item $ \delta _i ^+ \ = \ \mathcal{F}_{\delta}(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+,\ \mathcal{P}_i) $ donne le temps d'ex\'ecution 552
de la t\^ache en fonction de la pr\'ecision voulue, du d\'ebit et des paramètres internes. 553
\item $ \pi _i ^+ \ = \ \mathcal{F}_{p}(\pi_i^-,\ \mathcal{P}_i) $, la fonction $F_p$ donne la pr\'ecision en sortie selon la pr\'ecision de d\'epart 554
et les paramètres internes de la t\^ache. 555
\item $d_i^+\ =\ \mathcal{F}_d(d_i^-, \mathcal{P}_i)$, la fonction $F_d$ donne le d\'ebit sortant de la t\^ache en fonction du d\'ebit 556
sortant et des variables internes de la t\^ache. 557
\item $A_i^+\ =\ \mathcal{F}_A(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+, \mathcal{P}_i)$ 558
\end{itemize} 559
Pour le moment, nous ne sommes pas capables de donner une d\'efinition g\'en\'erale de ces fonctions. Mais en revanche, 560
sur quelques exemples simples (cf. \ref{def-contraintes}), nous parvenons à donner une \'evaluation de ces fonctions. 561
562
Maintenant que nous avons donn\'e toutes les notations utiles, nous allons \'enoncer des contraintes relatives à notre problème. Soit 563
un DGA $G(V,\ E)$, on a pour toutes arêtes $(i, j)\ \in\ E$ les in\'equations suivantes : 564
565
\paragraph{Contrainte de pr\'ecision :} 566
Cette in\'equation traduit la contrainte de pr\'ecision d'une t\^ache à l'autre : 567
\begin{align*} 568
\pi _i ^+ \geq \pi _j ^- 569
\end{align*} 570
571
\paragraph{Contrainte de d\'ebit :} 572
Cette in\'equation traduit la contrainte de d\'ebit d'une t\^ache à l'autre : 573
\begin{align*} 574
d _i ^+ = q _j ^- * (f_i + (1 / s_j) ) & \text{ où } s_j \text{ est une valeur positive de temporisation de la t\^ache} 575
\end{align*} 576
577
\paragraph{Contrainte de synchronisation :} 578
Il s'agit de la contrainte qui impose que si à un moment du traitement, le DAG se s\'epare en plusieurs branches parallèles 579
et qu'elles se rejoignent plus tard, la somme des latences sur chacune des branches soit la même. 580
Plus formellement, s'il existe plusieurs chemins disjoints, partant de la t\^ache $s$ et allant à la t\^ache de $f$ alors : 581
\begin{align*} 582
\forall \text{ chemin } \mathcal{C}1(s, .., f), 583
\forall \text{ chemin } \mathcal{C}2(s, .., f) 584
\text{ tel que } \mathcal{C}1 \neq \mathcal{C}2 585
\Rightarrow 586
\sum _{i} ^{i \in \mathcal{C}1} \delta_i = \sum _{i} ^{i \in \mathcal{C}2} \delta_i 587
\end{align*} 588
589
\paragraph{Contrainte de place :} 590
Cette in\'equation traduit la contrainte de place dans le FPGA. La taille max de la puce FPGA est nomm\'e $\mathcal{A}_{FPGA}$ : 591
ifcs2018_journal.tex
Diff comments   View file @ c9c460c
1 % fusionner max rejection a surface donnee v.s minimiser surface a rejection donnee
2 % demontrer comment la quantification rejette du bruit vers les hautes frequences => 6 dB de
3 % rejection par bit et perte si moins de bits que rejection/6
4 % developper programme lineaire en incluant le decalage de bits
5 % insister que avant on etait synthetisable mais pas implementable, alors que maintenant on
6 % implemente et on demontre que ca tourne
7 % gwen : pourquoi le FIR est desormais implementable et ne l'etait pas meme sur zedboard->new FIR ?
8 % Gwen : peut-on faire un vrai banc de bruit de phase avec ce FIR, ie ajouter ADC, NCO et mixer
9 % (zedboard ou redpit)
10
11 % ajouter pyramide "juste"
12 % label schema : verifier que "argumenter de la cascade de FIR" est fait
13
\documentclass[a4paper,conference]{IEEEtran/IEEEtran} 1 14 \documentclass[a4paper,conference]{IEEEtran/IEEEtran}
\usepackage{graphicx,color,hyperref} 2 15 \usepackage{graphicx,color,hyperref}
\usepackage{amsfonts} 3 16 \usepackage{amsfonts}
\usepackage{amsthm} 4 17 \usepackage{amsthm}
\usepackage{amssymb} 5 18 \usepackage{amssymb}
\usepackage{amsmath} 6 19 \usepackage{amsmath}
\usepackage{algorithm2e} 7 20 \usepackage{algorithm2e}
\usepackage{url,balance} 8 21 \usepackage{url,balance}
\usepackage[normalem]{ulem} 9 22 \usepackage[normalem]{ulem}
\usepackage{tikz} 10 23 \usepackage{tikz}
\usetikzlibrary{positioning,fit} 11 24 \usetikzlibrary{positioning,fit}
\usepackage{multirow} 12 25 \usepackage{multirow}
\usepackage{scalefnt} 13 26 \usepackage{scalefnt}
14 27
% correct bad hyphenation here 15 28 % correct bad hyphenation here
\hyphenation{op-tical net-works semi-conduc-tor} 16 29 \hyphenation{op-tical net-works semi-conduc-tor}
\textheight=26cm 17 30 \textheight=26cm
\setlength{\footskip}{30pt} 18 31 \setlength{\footskip}{30pt}
\pagenumbering{gobble} 19 32 \pagenumbering{gobble}
\begin{document} 20 33 \begin{document}
\title{Filter optimization for real time digital processing of radiofrequency signals: application 21 34 \title{Filter optimization for real time digital processing of radiofrequency signals: application
to oscillator metrology} 22 35 to oscillator metrology}
23 36
\author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2}, 24 37 \author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2},
G. Goavec-M\'erou\IEEEauthorrefmark{1}, 25 38 G. Goavec-M\'erou\IEEEauthorrefmark{1},
P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}} 26 39 P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}}
\IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France } 27 40 \IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France }
\IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\ 28 41 \IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\
Email: \{pyb2,jmfriedt\}@femto-st.fr} 29 42 Email: \{pyb2,jmfriedt\}@femto-st.fr}
} 30 43 }
\maketitle 31 44 \maketitle
\thispagestyle{plain} 32 45 \thispagestyle{plain}
\pagestyle{plain} 33 46 \pagestyle{plain}
\newtheorem{definition}{Definition} 34 47 \newtheorem{definition}{Definition}
35 48
\begin{abstract} 36 49 \begin{abstract}
Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to 37 50 Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to
radiofrequency signal processing. Applied to oscillator characterization in the context 38 51 radiofrequency signal processing. Applied to oscillator characterization in the context
of ultrastable clocks, stringent filtering requirements are defined by spurious signal or 39 52 of ultrastable clocks, stringent filtering requirements are defined by spurious signal or
noise rejection needs. Since real time radiofrequency processing must be performed in a 40 53 noise rejection needs. Since real time radiofrequency processing must be performed in a
Field Programmable Array to meet timing constraints, we investigate optimization strategies 41 54 Field Programmable Array to meet timing constraints, we investigate optimization strategies
to design filters meeting rejection characteristics while limiting the hardware resources 42 55 to design filters meeting rejection characteristics while limiting the hardware resources
required and keeping timing constraints within the targeted measurement bandwidths. 43 56 required and keeping timing constraints within the targeted measurement bandwidths.
\end{abstract} 44 57 \end{abstract}
45 58
\begin{IEEEkeywords} 46 59 \begin{IEEEkeywords}
Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter 47 60 Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter
\end{IEEEkeywords} 48 61 \end{IEEEkeywords}
49 62
\section{Digital signal processing of ultrastable clock signals} 50 63 \section{Digital signal processing of ultrastable clock signals}
51 64
Analog oscillator phase noise characteristics are classically performed by downconverting 52 65 Analog oscillator phase noise characteristics are classically performed by downconverting
the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband, 53 66 the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband,
followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In 54 67 followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In
a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by 55 68 a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by
multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}. 56 69 multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}.
57 70
\begin{figure}[h!tb] 58 71 \begin{figure}[h!tb]
\begin{center} 59 72 \begin{center}
\includegraphics[width=.8\linewidth]{images/schema} 60 73 \includegraphics[width=.8\linewidth]{images/schema}
\end{center} 61 74 \end{center}
\caption{Fully digital oscillator phase noise characterization: the Device Under Test 62 75 \caption{Fully digital oscillator phase noise characterization: the Device Under Test
(DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and 63 76 (DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and
downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals 64 77 downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals
and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite 65 78 and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite
Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays 66 79 Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays
the spectral characteristics of the phase fluctuations.} 67 80 the spectral characteristics of the phase fluctuations.}
\label{schema} 68 81 \label{schema}
\end{figure} 69 82 \end{figure}
70 83
As with the analog mixer, 71 84 As with the analog mixer,
the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as 72 85 the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as
well as the generation of the frequency sum signal in addition to the frequency difference. 73 86 well as the generation of the frequency sum signal in addition to the frequency difference.
These unwanted spectral characteristics must be rejected before decimating the data stream 74 87 These unwanted spectral characteristics must be rejected before decimating the data stream
for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the 75 88 for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the
downconverter 76 89 downconverter
and the decimation processing blocks are core characteristics of an oscillator characterization 77 90 and the decimation processing blocks are core characteristics of an oscillator characterization
system, and must reject out-of-band signals below the targeted phase noise -- typically in the 78 91 system, and must reject out-of-band signals below the targeted phase noise -- typically in the
sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will 79 92 sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will
use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency 80 93 use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency
datastream: optimizing the performance of the filter while reducing the needed resources is 81 94 datastream: optimizing the performance of the filter while reducing the needed resources is
hence tackled in a systematic approach using optimization techniques. Most significantly, we 82 95 hence tackled in a systematic approach using optimization techniques. Most significantly, we
tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with 83 96 tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with
tunable number of coefficients and tunable number of bits representing the coefficients and the 84 97 tunable number of coefficients and tunable number of bits representing the coefficients and the
data being processed. 85 98 data being processed.
86 99
\section{Finite impulse response filter} 87 100 \section{Finite impulse response filter}
88 101
We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined 89 102 We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined
by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the 90 103 by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the
outputs $y_k$ 91 104 outputs $y_k$
\begin{align} 92 105 \begin{align}
y_n=\sum_{k=0}^N b_k x_{n-k} 93 106 y_n=\sum_{k=0}^N b_k x_{n-k}
\label{eq:fir_equation} 94 107 \label{eq:fir_equation}
\end{align} 95 108 \end{align}
96 109
As opposed to an implementation on a general purpose processor in which word size is defined by the 97 110 As opposed to an implementation on a general purpose processor in which word size is defined by the
processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since 98 111 processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since
not only the coefficient values and number of taps must be defined, but also the number of bits 99 112 not only the coefficient values and number of taps must be defined, but also the number of bits
defining the coefficients and the sample size. For this reason, and because we consider pipeline 100 113 defining the coefficients and the sample size. For this reason, and because we consider pipeline
processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency 101 114 processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency
signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but 102 115 signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level. 103 116 the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level.
Since latency is not an issue in a openloop phase noise characterization instrument, the large 104 117 Since latency is not an issue in a openloop phase noise characterization instrument, the large
numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter, 105 118 numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
is not considered as an issue as would be in a closed loop system. 106 119 is not considered as an issue as would be in a closed loop system.
107 120
The coefficients are classically expressed as floating point values. However, this binary 108 121 The coefficients are classically expressed as floating point values. However, this binary
number representation is not efficient for fast arithmetic computation by an FPGA. Instead, 109 122 number representation is not efficient for fast arithmetic computation by an FPGA. Instead,
we select to quantify these floating point values into integer values. This quantization 110 123 we select to quantify these floating point values into integer values. This quantization
will result in some precision loss. 111 124 will result in some precision loss.
112 125
\begin{figure}[h!tb] 113 126 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/zero_values} 114 127 \includegraphics[width=\linewidth]{images/zero_values}
\caption{Impact of the quantization resolution of the coefficients: the quantization is 115 128 \caption{Impact of the quantization resolution of the coefficients: the quantization is
set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting 116 129 set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting
the 30~first and 30~last coefficients out of the initial 128~band-pass 117 130 the 30~first and 30~last coefficients out of the initial 128~band-pass
filter coefficients to 0 (red dots).} 118 131 filter coefficients to 0 (red dots).}
\label{float_vs_int} 119 132 \label{float_vs_int}
\end{figure} 120 133 \end{figure}
121 134
The tradeoff between quantization resolution and number of coefficients when considering 122 135 The tradeoff between quantization resolution and number of coefficients when considering
integer operations is not trivial. As an illustration of the issue related to the 123 136 integer operations is not trivial. As an illustration of the issue related to the
relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits 124 137 relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits
a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon 125 138 a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon
quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the 126 139 quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the
taps become null, making the large number of coefficients irrelevant and allowing to save 127 140 taps become null, making the large number of coefficients irrelevant and allowing to save
processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources 128 141 processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources
to reach a given rejection level, or maximizing out of band rejection for a given computational 129 142 to reach a given rejection level, or maximizing out of band rejection for a given computational
resource, will drive the investigation on cascading filters designed with varying tap resolution 130 143 resource, will drive the investigation on cascading filters designed with varying tap resolution
and tap length, as will be shown in the next section. Indeed, our development strategy closely 131 144 and tap length, as will be shown in the next section. Indeed, our development strategy closely
follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards} 132 145 follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards}
in which basic blocks are defined and characterized before being assembled \cite{hide} 133 146 in which basic blocks are defined and characterized before being assembled \cite{hide}
in a complete processing chain. In our case, assembling the filter blocks is a simpler block 134 147 in a complete processing chain. In our case, assembling the filter blocks is a simpler block
combination process since we assume a single value to be processed and a single value to be 135 148 combination process since we assume a single value to be processed and a single value to be
generated at each clock cycle. The FIR filters will not be considered to decimate in the 136 149 generated at each clock cycle. The FIR filters will not be considered to decimate in the
current implementation: the decimation is assumed to be located after the FIR cascade at the 137 150 current implementation: the decimation is assumed to be located after the FIR cascade at the
moment. 138 151 moment.
139 152
\section{Methodology description} 140 153 \section{Methodology description}
We want create a new methodology to develop any Digital Signal Processing (DSP) chain 141 154 We want create a new methodology to develop any Digital Signal Processing (DSP) chain
and for any hardware platform (Altera, Xilinx...). To do this we have defined an 142 155 and for any hardware platform (Altera, Xilinx...). To do this we have defined an
abstract model to represent some basic operations of DSP. 143 156 abstract model to represent some basic operations of DSP.
144 157
For the moment, we are focused on only two operations: the filtering and the shifting of data. 145 158 For the moment, we are focused on only two operations: the filtering and the shifting of data.
We have chosen this basic operation because the shifting and the filtering have already be studied in 146 159 We have chosen this basic operation because the shifting and the filtering have already be studied in
lot of works \cite{lim_1996, lim_1988, young_1992, smith_1998} hence it will be easier 147 160 lot of works \cite{lim_1996, lim_1988, young_1992, smith_1998} hence it will be easier
to check and validate our results. 148 161 to check and validate our results.
149 162
However having only two operations is insufficient to work with complex DSP but 150 163 However having only two operations is insufficient to work with complex DSP but
in this paper we only want demonstrate the relevance and the efficiency of our approach. 151 164 in this paper we only want demonstrate the relevance and the efficiency of our approach.
In future work it will be possible to add more operations and we are able to 152 165 In future work it will be possible to add more operations and we are able to
model any DSP chain. 153 166 model any DSP chain.
154 167
We will apply our methodology on very simple DSP chain. We generate a digital signal 155 168 We will apply our methodology on very simple DSP chain. We generate a digital signal
thanks at generator of Pseudo-Random Number (PRN) or thanks at an Analog to Digital 156 169 thanks at generator of Pseudo-Random Number (PRN) or thanks at an Analog to Digital
Converter (ADC). Once we have a digital signal, we filter it to decrease the noise level. 157 170 Converter (ADC). Once we have a digital signal, we filter it to decrease the noise level.
Finally we stored some burst of filtered samples before post-processing it. 158 171 Finally we stored some burst of filtered samples before post-processing it.
% TODO: faire un schéma 159 172 % TODO: faire un schéma
In this particular case, we want optimize the filtering step to have the best noise 160 173 In this particular case, we want optimize the filtering step to have the best noise
rejection for constrain number of resource or to have the minimal resources 161 174 rejection for constrain number of resource or to have the minimal resources
consumption for a given rejection objective. 162 175 consumption for a given rejection objective.
163 176
The first step of our approach is to model the DSP chain and since we just optimize 164 177 The first step of our approach is to model the DSP chain and since we just optimize
the filtering, we have not modeling the PRN generator or the ADC. The filtering can be 165 178 the filtering, we have not modeling the PRN generator or the ADC. The filtering can be
done by two ways. The first one we use only one FIR filter with lot of coefficients 166 179 done by two ways. The first one we use only one FIR filter with lot of coefficients
to rejection the noise, we called this approach a monolithic approach. And the second one 167 180 to rejection the noise, we called this approach a monolithic approach. And the second one
we select different FIR filters with less coefficients the monolithic filter and we cascaded 168 181 we select different FIR filters with less coefficients the monolithic filter and we cascaded
it to filtering the signal. 169 182 it to filtering the signal.
170 183
After each filter we leave the possibility of shifting the filtered data to consume 171 184 After each filter we leave the possibility of shifting the filtered data to consume
less resources. Hence in the case of cascaded filter, we define a stage as a filter 172 185 less resources. Hence in the case of cascaded filter, we define a stage as a filter
and a shifter (the shift could be omitted if we do not need to divide the filtered data). 173 186 and a shifter (the shift could be omitted if we do not need to divide the filtered data).
174 187
\subsection{Model of a FIR filter} 175 188 \subsection{Model of a FIR filter}
A cascade of filter are composed of $n$ stage. In stage $i$ ($1 \leq i \leq n$) 176 189 A cascade of filter are composed of $n$ stage. In stage $i$ ($1 \leq i \leq n$)
the FIR has $C_i$ coefficients and each coefficients are integer values with $\pi^C_i$ 177 190 the FIR has $C_i$ coefficients and each coefficients are integer values with $\pi^C_i$
bits and the filtered data are shifted of $\pi^S_i$ bits. We define also $\pi^-_i$ as 178 191 bits and the filtered data are shifted of $\pi^S_i$ bits. We define also $\pi^-_i$ as
the size of input data and $\pi^+_i$ as the size of output data. The figure~\ref{fig:fir_stage} 179 192 the size of input data and $\pi^+_i$ as the size of output data. The figure~\ref{fig:fir_stage}
shows a filtering stage. 180 193 shows a filtering stage.
181 194
\begin{figure} 182 195 \begin{figure}
\centering 183 196 \centering
\begin{tikzpicture}[node distance=2cm] 184 197 \begin{tikzpicture}[node distance=2cm]
\node[draw,minimum size=1.3cm] (FIR) { $C_i, \pi_i^C$ } ; 185 198 \node[draw,minimum size=1.3cm] (FIR) { $C_i, \pi_i^C$ } ;
\node[draw,minimum size=1.3cm] (Shift) [right of=FIR, ] { $\pi_i^S$ } ; 186 199 \node[draw,minimum size=1.3cm] (Shift) [right of=FIR, ] { $\pi_i^S$ } ;
\node (Start) [left of=FIR] { } ; 187 200 \node (Start) [left of=FIR] { } ;
\node (End) [right of=Shift] { } ; 188 201 \node (End) [right of=Shift] { } ;
189 202
\node[draw,fit=(FIR) (Shift)] (Filter) { } ; 190 203 \node[draw,fit=(FIR) (Shift)] (Filter) { } ;
191 204
\draw[->] (Start) edge node [above] { $\pi_i^-$ } (FIR) ; 192 205 \draw[->] (Start) edge node [above] { $\pi_i^-$ } (FIR) ;
\draw[->] (FIR) -- (Shift) ; 193 206 \draw[->] (FIR) -- (Shift) ;
\draw[->] (Shift) edge node [above] { $\pi_i^+$ } (End) ; 194 207 \draw[->] (Shift) edge node [above] { $\pi_i^+$ } (End) ;
\end{tikzpicture} 195 208 \end{tikzpicture}
\caption{A single filter is composed of a FIR (on the left) and a Shifter (on the right)} 196 209 \caption{A single filter is composed of a FIR (on the left) and a Shifter (on the right)}
\label{fig:fir_stage} 197 210 \label{fig:fir_stage}
\end{figure} 198 211 \end{figure}
199 212
FIR $i$ can reject $F(C_i, \pi_i^C)$ dB. $F$ is determined numerically. 200 213 FIR $i$ can reject $F(C_i, \pi_i^C)$ dB. $F$ is determined numerically.
To measure this rejection, we use GNU Octave software to design FIR filter coefficients thanks to two 201 214 To measure this rejection, we use GNU Octave software to design FIR filter coefficients thanks to two
algorithms (\texttt{firls} and \texttt{fir1}). 202 215 algorithms (\texttt{firls} and \texttt{fir1}).
For each configuration $(C_i, \pi_i^C)$, we first create a FIR with floating point coefficients and a given $C_i$ number of coefficients. 203 216 For each configuration $(C_i, \pi_i^C)$, we first create a FIR with floating point coefficients and a given $C_i$ number of coefficients.
Then, the floating point coefficients are discretized into integers. In order to ensure that the coefficients are coded on $\pi_i^C$~bits effectively, 204 217 Then, the floating point coefficients are discretized into integers. In order to ensure that the coefficients are coded on $\pi_i^C$~bits effectively,
the coefficients are normalized by their absolute maximum before being scaled to integer coefficients. 205 218 the coefficients are normalized by their absolute maximum before being scaled to integer coefficients.
At least one coefficient is coded on $\pi_i^C$~bits, and in practice only $b_{C_i/2}$ is coded on $\pi_i^C$~bits while the other are coded on very fewer bits. 206 219 At least one coefficient is coded on $\pi_i^C$~bits, and in practice only $b_{C_i/2}$ is coded on $\pi_i^C$~bits while the other are coded on very fewer bits.
207 220
With these coefficients, the \texttt{freqz} function is used to estimate the magnitude of the filter. 208 221 With these coefficients, the \texttt{freqz} function is used to estimate the magnitude of the filter.
Comparing the performance between FIRs requires however a unique criterion. As shown in figure~\ref{fig:fir_mag}, 209 222 Comparing the performance between FIRs requires however a unique criterion. As shown in figure~\ref{fig:fir_mag},
the FIR magnitude exhibits two parts. 210 223 the FIR magnitude exhibits two parts.
211 224
\begin{figure} 212 225 \begin{figure}
\centering 213 226 \centering
\begin{tikzpicture}[scale=0.3] 214 227 \begin{tikzpicture}[scale=0.3]
\draw[<->] (0,15) -- (0,0) -- (21,0) ; 215 228 \draw[<->] (0,15) -- (0,0) -- (21,0) ;
\draw[thick] (0,12) -- (8,12) -- (20,0) ; 216 229 \draw[thick] (0,12) -- (8,12) -- (20,0) ;
217 230
\draw (0,14) node [left] { $P$ } ; 218 231 \draw (0,14) node [left] { $P$ } ;
\draw (20,0) node [below] { $f$ } ; 219 232 \draw (20,0) node [below] { $f$ } ;
220 233
\draw[>=latex,<->] (0,14) -- (8,14) ; 221 234 \draw[>=latex,<->] (0,14) -- (8,14) ;
\draw (4,14) node [above] { passband } node [below] { $40\%$ } ; 222 235 \draw (4,14) node [above] { passband } node [below] { $40\%$ } ;
223 236
\draw[>=latex,<->] (8,14) -- (12,14) ; 224 237 \draw[>=latex,<->] (8,14) -- (12,14) ;
\draw (10,14) node [above] { transition } node [below] { $20\%$ } ; 225 238 \draw (10,14) node [above] { transition } node [below] { $20\%$ } ;
226 239
\draw[>=latex,<->] (12,14) -- (20,14) ; 227 240 \draw[>=latex,<->] (12,14) -- (20,14) ;
\draw (16,14) node [above] { stopband } node [below] { $40\%$ } ; 228 241 \draw (16,14) node [above] { stopband } node [below] { $40\%$ } ;
229 242
\draw[>=latex,<->] (16,12) -- (16,8) ; 230 243 \draw[>=latex,<->] (16,12) -- (16,8) ;
\draw (16,10) node [right] { rejection } ; 231 244 \draw (16,10) node [right] { rejection } ;
232 245
\draw[dashed] (8,-1) -- (8,14) ; 233 246 \draw[dashed] (8,-1) -- (8,14) ;
\draw[dashed] (12,-1) -- (12,14) ; 234 247 \draw[dashed] (12,-1) -- (12,14) ;
235 248
\draw[dashed] (8,12) -- (16,12) ; 236 249 \draw[dashed] (8,12) -- (16,12) ;
\draw[dashed] (12,8) -- (16,8) ; 237 250 \draw[dashed] (12,8) -- (16,8) ;
238 251
\end{tikzpicture} 239 252 \end{tikzpicture}
240 253
% \includegraphics[width=.5\linewidth]{images/fir_magnitude} 241 254 % \includegraphics[width=.5\linewidth]{images/fir_magnitude}
\caption{Shape of the filter transmitted power $P$ as a function of frequency $f$: 242 255 \caption{Shape of the filter transmitted power $P$ as a function of frequency $f$:
the passband is considered to occupy the initial 40\% of the Nyquist frequency range, 243 256 the passband is considered to occupy the initial 40\% of the Nyquist frequency range,
the stopband the last 40\%, allowing 20\% transition width.} 244 257 the stopband the last 40\%, allowing 20\% transition width.}
\label{fig:fir_mag} 245 258 \label{fig:fir_mag}
\end{figure} 246 259 \end{figure}
247 260
In the transition band, the behavior of the filter is left free, we only care about the passband and the stopband. 248 261 In the transition band, the behavior of the filter is left free, we only care about the passband and the stopband.
Our first criterion considers the mean value of the stopband rejection, as shown in figure~\ref{fig:mean_criterion}. This criterion does not work because we do not consider the shape of the passband. 249 262 Our first criterion considers the mean value of the stopband rejection, as shown in figure~\ref{fig:mean_criterion}. This criterion does not work because we do not consider the shape of the passband.
A second criterion considers the maximum rejection within the stopband minus the mean of the absolute value of passband rejection. With this criterion, the results are significantly improved as shown in figure~\ref{fig:custom_criterion}. 250 263 A second criterion considers the maximum rejection within the stopband minus the mean of the absolute value of passband rejection. With this criterion, the results are significantly improved as shown in figure~\ref{fig:custom_criterion}.
251 264
\begin{figure} 252 265 \begin{figure}
\centering 253 266 \centering
\includegraphics[width=\linewidth]{images/colored_mean_criterion} 254 267 \includegraphics[width=\linewidth]{images/colored_mean_criterion}
\caption{Mean criterion comparison between monolithic filter and cascade filters} 255 268 \caption{Mean criterion comparison between monolithic filter and cascade filters}
\label{fig:mean_criterion} 256 269 \label{fig:mean_criterion}
\end{figure} 257 270 \end{figure}
258 271
\begin{figure} 259 272 \begin{figure}
\centering 260 273 \centering
\includegraphics[width=\linewidth]{images/colored_custom_criterion} 261 274 \includegraphics[width=\linewidth]{images/colored_custom_criterion}
\caption{Custom criterion comparison between monolithic filter and cascade filters} 262 275 \caption{Custom criterion comparison between monolithic filter and cascade filters}
\label{fig:custom_criterion} 263 276 \label{fig:custom_criterion}
\end{figure} 264 277 \end{figure}
265 278
Although we have a efficient criterion to estimate the rejection of one set of coefficient 266 279 Although we have a efficient criterion to estimate the rejection of one set of coefficient
we have a problem when we sum two or more criterion. If the FIR filter coefficients are the same 267 280 we have a problem when we sum two or more criterion. If the FIR filter coefficients are the same
between the stage, we have: 268 281 between the stage, we have:
$$F_{total} = F_1 + F_2$$ 269 282 $$F_{total} = F_1 + F_2$$
But when we choose two different set of coefficient, the previous equality are not 270 283 But when we choose two different set of coefficient, the previous equality are not
true. The figure~\ref{fig:sum_rejection} illustrates the problem. The red and blue curves 271 284 true. The figure~\ref{fig:sum_rejection} illustrates the problem. The red and blue curves
are two different filter coefficient and we can see that their maximum on the stopband 272 285 are two different filter coefficient and we can see that their maximum on the stopband
are not at the same frequency. So when we sum the rejection criteria (the dotted yellow line) 273 286 are not at the same frequency. So when we sum the rejection criteria (the dotted yellow line)
we do not meet the dashed yellow line. Define the rejection of cascaded filters 274 287 we do not meet the dashed yellow line. Define the rejection of cascaded filters
is more difficult than just take the summation between all the rejection criteria of each filter. 275 288 is more difficult than just take the summation between all the rejection criteria of each filter.
However this summation gives us an upper bound for rejection although in fact we obtain 276 289 However this summation gives us an upper bound for rejection although in fact we obtain
better rejection than expected. 277 290 better rejection than expected.
278 291
\begin{figure} 279 292 \begin{figure}
\centering 280 293 \centering
\includegraphics[width=\linewidth]{images/cascaded_criterion} 281 294 \includegraphics[width=\linewidth]{images/cascaded_criterion}
\caption{Rejection of two cascaded filters} 282 295 \caption{Rejection of two cascaded filters}
\label{fig:sum_rejection} 283 296 \label{fig:sum_rejection}
\end{figure} 284 297 \end{figure}
285 298
The first problem we address is to maximize the rejection under bounded silicon area 286 299 The first problem we address is to maximize the rejection under bounded silicon area
and feasibility constraints. Variable $a_i$ is the area taken by filter~$i$ 287 300 and feasibility constraints. Variable $a_i$ is the area taken by filter~$i$
(in arbitrary unit). Variable $r_i$ is the rejection of filter~$i$ (in dB). 288 301 (in arbitrary unit). Variable $r_i$ is the rejection of filter~$i$ (in dB).
Constant $\mathcal{A}$ is the total available area. We model our problem as follows: 289 302 Constant $\mathcal{A}$ is the total available area. We model our problem as follows:
290 303
Finally we can describe our abstract model with following expressions : 291 304 Finally we can describe our abstract model with following expressions :
\begin{align} 292 305 \begin{align}
\text{Maximize } & \sum_{i=1}^n r_i \notag \\ 293 306 \text{Maximize } & \sum_{i=1}^n r_i \notag \\
\sum_{i=1}^n a_i & \leq \mathcal{A} & \label{eq:area} \\ 294 307 \sum_{i=1}^n a_i & \leq \mathcal{A} & \label{eq:area} \\
a_i & = C_i \times (\pi_i^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef} \\ 295 308 a_i & = C_i \times (\pi_i^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef} \\
r_i & = F(C_i, \pi_i^C), & \forall i \in [1, n] \label{eq:rejectiondef} \\ 296 309 r_i & = F(C_i, \pi_i^C), & \forall i \in [1, n] \label{eq:rejectiondef} \\
\pi_i^+ & = \pi_i^- + \pi_i^C - \pi_i^S, & \forall i \in [1, n] \label{eq:bits} \\ 297 310 \pi_i^+ & = \pi_i^- + \pi_i^C - \pi_i^S, & \forall i \in [1, n] \label{eq:bits} \\
\pi_{i - 1}^+ & = \pi_i^-, & \forall i \in [2, n] \label{eq:inout} \\ 298 311 \pi_{i - 1}^+ & = \pi_i^-, & \forall i \in [2, n] \label{eq:inout} \\
\pi_i^+ & \geq 1 + \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right), & \forall i \in [1, n] \label{eq:maxshift} \\ 299 312 \pi_i^+ & \geq 1 + \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right), & \forall i \in [1, n] \label{eq:maxshift} \\
\pi_1^- &= \Pi^I \label{eq:init} 300 313 \pi_1^- &= \Pi^I \label{eq:init}
\end{align} 301 314 \end{align}
302 315
Equation~\ref{eq:area} states that the total area taken by the filters must be 303 316 Equation~\ref{eq:area} states that the total area taken by the filters must be
less than the available area. Equation~\ref{eq:areadef} gives the definition of 304 317 less than the available area. Equation~\ref{eq:areadef} gives the definition of
the area for a filter. More precisely, it is the area of the FIR as the Shifter 305 318 the area for a filter. More precisely, it is the area of the FIR as the Shifter
does not need any circuitry. We consider that the FIR needs $C_i$ registers of size 306 319 does not need any circuitry. We consider that the FIR needs $C_i$ registers of size
$\pi_i^C + \pi_i^-$~bits to store the results of the multiplications of the 307 320 $\pi_i^C + \pi_i^-$~bits to store the results of the multiplications of the
input data and the coefficients. Equation~\ref{eq:rejectiondef} gives the 308 321 input data and the coefficients. Equation~\ref{eq:rejectiondef} gives the
definition of the rejection of the filter thanks to function~$F$ that we defined 309 322 definition of the rejection of the filter thanks to function~$F$ that we defined
previously. The Shifter does not introduce negative rejection as we explain later, 310 323 previously. The Shifter does not introduce negative rejection as we explain later,
so the rejection only comes from the FIR. Equation~\ref{eq:bits} states the 311 324 so the rejection only comes from the FIR. Equation~\ref{eq:bits} states the
relation between $\pi_i^+$ and $\pi_i^-$. The multiplications in the FIR add 312 325 relation between $\pi_i^+$ and $\pi_i^-$. The multiplications in the FIR add
$\pi_i^C$ bits as most coefficients are close to zero, and the Shifter removes 313 326 $\pi_i^C$ bits as most coefficients are close to zero, and the Shifter removes
$\pi_i^S$ bits. Equation~\ref{eq:inout} states that the output number of bits of 314 327 $\pi_i^S$ bits. Equation~\ref{eq:inout} states that the output number of bits of
a filter is the same as the input number of bits of the next filter. 315 328 a filter is the same as the input number of bits of the next filter.
Equation~\ref{eq:maxshift} ensures that the Shifter does not introduce negative 316 329 Equation~\ref{eq:maxshift} ensures that the Shifter does not introduce negative
rejection. Indeed, the results of the FIR can be right shifted without compromising 317 330 rejection. Indeed, the results of the FIR can be right shifted without compromising
the quality of the rejection until a threshold. Each bit of the output data 318 331 the quality of the rejection until a threshold. Each bit of the output data
increases the maximum rejection level of 6~dB. We add one to take the sign bit 319 332 increases the maximum rejection level of 6~dB. We add one to take the sign bit
into account. If equation~\ref{eq:maxshift} was not present, the Shifter could 320 333 into account. If equation~\ref{eq:maxshift} was not present, the Shifter could
shift too much and introduce some noise in the output data. Each supplementary 321 334 shift too much and introduce some noise in the output data. Each supplementary
shift bit would cause 6~dB of noise. A totally equivalent equation is: 322 335 shift bit would cause 6~dB of noise. A totally equivalent equation is:
$\pi_i^S \leq \pi_i^- + \pi_i^C - 1 - \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right) $. 323 336 $\pi_i^S \leq \pi_i^- + \pi_i^C - 1 - \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right) $.
Finally, equation~\ref{eq:init} gives the global input's number of bits. 324 337 Finally, equation~\ref{eq:init} gives the global input's number of bits.
325 338
This model is non-linear and even non-quadratic, as $F$ does not have a known 326 339 This model is non-linear and even non-quadratic, as $F$ does not have a known
linear or quadratic expression. We introduce $p$ FIR configurations 327 340 linear or quadratic expression. We introduce $p$ FIR configurations
$(C_{ij}, \pi_{ij}^C), 1 \leq j \leq p$ that are constants. We define binary 328 341 $(C_{ij}, \pi_{ij}^C), 1 \leq j \leq p$ that are constants. We define binary
variable $\delta_{ij}$ that has value 1 if stage~$i$ is in configuration~$j$ 329 342 variable $\delta_{ij}$ that has value 1 if stage~$i$ is in configuration~$j$
and 0 otherwise. The new equations are as follows: 330 343 and 0 otherwise. The new equations are as follows:
331 344
\begin{align} 332 345 \begin{align}
a_i & = \sum_{j=1}^p \delta_{ij} \times C_{ij} \times (\pi_{ij}^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef2} \\ 333 346 a_i & = \sum_{j=1}^p \delta_{ij} \times C_{ij} \times (\pi_{ij}^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef2} \\
r_i & = \sum_{j=1}^p \delta_{ij} \times F(C_{ij}, \pi_{ij}^C), & \forall i \in [1, n] \label{eq:rejectiondef2} \\ 334 347 r_i & = \sum_{j=1}^p \delta_{ij} \times F(C_{ij}, \pi_{ij}^C), & \forall i \in [1, n] \label{eq:rejectiondef2} \\
\pi_i^+ & = \pi_i^- + \left(\sum_{j=1}^p \delta_{ij} \pi_{ij}^C\right) - \pi_i^S, & \forall i \in [1, n] \label{eq:bits2} \\ 335 348 \pi_i^+ & = \pi_i^- + \left(\sum_{j=1}^p \delta_{ij} \pi_{ij}^C\right) - \pi_i^S, & \forall i \in [1, n] \label{eq:bits2} \\
\sum_{j=1}^p \delta_{ij} & \leq 1, & \forall i \in [1, n] \label{eq:config} 336 349 \sum_{j=1}^p \delta_{ij} & \leq 1, & \forall i \in [1, n] \label{eq:config}
\end{align} 337 350 \end{align}
338 351
Equations \ref{eq:areadef2}, \ref{eq:rejectiondef2} and \ref{eq:bits2} replace 339 352 Equations \ref{eq:areadef2}, \ref{eq:rejectiondef2} and \ref{eq:bits2} replace
respectively equations \ref{eq:areadef}, \ref{eq:rejectiondef} and \ref{eq:bits}. 340 353 respectively equations \ref{eq:areadef}, \ref{eq:rejectiondef} and \ref{eq:bits}.
Equation~\ref{eq:config} states that for each stage, a single configuration is chosen at most. 341 354 Equation~\ref{eq:config} states that for each stage, a single configuration is chosen at most.
342 355
This modified model is quadratic, and it can be linearised if necessary. The Gurobi 343 356 This modified model is quadratic, and it can be linearised if necessary. The Gurobi
(\url{www.gurobi.com}) optimization software is used to solve this quadratic 344 357 (\url{www.gurobi.com}) optimization software is used to solve this quadratic
model, and since Gurobi is able to linearize, the model is left as is. This model 345 358 model, and since Gurobi is able to linearize, the model is left as is. This model
has $O(np)$ variables and $O(n)$ constraints. 346 359 has $O(np)$ variables and $O(n)$ constraints.
347 360
The section~\ref{sec:fixed_area} shows the results for the first version of quadratic program but the section~\ref{sec:fixed_rej} 348 361 The section~\ref{sec:fixed_area} shows the results for the first version of quadratic program but the section~\ref{sec:fixed_rej}
presents the results for the complementary problem. In this case we want 349 362 presents the results for the complementary problem. In this case we want
minimize the occupied area for a targeted rejection level. Hence we have replace 350 363 minimize the occupied area for a targeted rejection level. Hence we have replace
the objective function with: 351 364 the objective function with:
\begin{align} 352 365 \begin{align}
\text{Minimize } & \sum_{i=1}^n a_i \notag 353 366 \text{Minimize } & \sum_{i=1}^n a_i \notag
\end{align} 354 367 \end{align}
We adapt our constraints of quadratic program to replace the equation \ref{eq:area} 355 368 We adapt our constraints of quadratic program to replace the equation \ref{eq:area}
by the equation \ref{eq:rejection_min} where $\mathcal{R}$ is the minimal 356 369 by the equation \ref{eq:rejection_min} where $\mathcal{R}$ is the minimal
rejection required. 357 370 rejection required.
358 371
\begin{align} 359 372 \begin{align}
\sum_{i=1}^n r_i & \geq \mathcal{R} & \label{eq:rejection_min} 360 373 \sum_{i=1}^n r_i & \geq \mathcal{R} & \label{eq:rejection_min}
\end{align} 361 374 \end{align}
362 375
\section{Design workflow} 363 376 \section{Design workflow}
\label{sec:workflow} 364 377 \label{sec:workflow}
365 378
In this section, we describe the workflow to compute all the results presented in section~\ref{sec:fixed_area}. 366 379 In this section, we describe the workflow to compute all the results presented in section~\ref{sec:fixed_area}.
Figure~\ref{fig:workflow} shows the global workflow and the different steps involved in the computations of the results. 367 380 Figure~\ref{fig:workflow} shows the global workflow and the different steps involved in the computations of the results.
368 381
\begin{figure} 369 382 \begin{figure}
\centering 370 383 \centering
\begin{tikzpicture}[node distance=0.75cm and 2cm] 371 384 \begin{tikzpicture}[node distance=0.75cm and 2cm]
\node[draw,minimum size=1cm] (Solver) { Filter Solver } ; 372 385 \node[draw,minimum size=1cm] (Solver) { Filter Solver } ;
\node (Start) [left= 3cm of Solver] { } ; 373 386 \node (Start) [left= 3cm of Solver] { } ;
\node[draw,minimum size=1cm] (TCL) [right= of Solver] { TCL Script } ; 374 387 \node[draw,minimum size=1cm] (TCL) [right= of Solver] { TCL Script } ;
\node (Input) [above= of TCL] { } ; 375 388 \node (Input) [above= of TCL] { } ;
\node[draw,minimum size=1cm] (Deploy) [below= of Solver] { Deploy Script } ; 376 389 \node[draw,minimum size=1cm] (Deploy) [below= of Solver] { Deploy Script } ;
\node[draw,minimum size=1cm] (Bitstream) [below= of TCL] { Bitstream } ; 377 390 \node[draw,minimum size=1cm] (Bitstream) [below= of TCL] { Bitstream } ;
\node[draw,minimum size=1cm,rounded corners] (Board) [below right= of Deploy] { Board } ; 378 391 \node[draw,minimum size=1cm,rounded corners] (Board) [below right= of Deploy] { Board } ;
\node[draw,minimum size=1cm] (Postproc) [below= of Deploy] { Post-Processing } ; 379 392 \node[draw,minimum size=1cm] (Postproc) [below= of Deploy] { Post-Processing } ;
\node (Results) [left= of Postproc] { } ; 380 393 \node (Results) [left= of Postproc] { } ;
381 394
\draw[->] (Start) edge node [above] { $\mathcal{A}, n, \Pi^I$ } node [below] { $(C_{ij}, \pi_{ij}^C), F$ } (Solver) ; 382 395 \draw[->] (Start) edge node [above] { $\mathcal{A}, n, \Pi^I$ } node [below] { $(C_{ij}, \pi_{ij}^C), F$ } (Solver) ;
\draw[->] (Input) edge node [left] { ADC or PRN } (TCL) ; 383 396 \draw[->] (Input) edge node [left] { ADC or PRN } (TCL) ;
\draw[->] (Solver) edge node [below] { (1a) } (TCL) ; 384 397 \draw[->] (Solver) edge node [below] { (1a) } (TCL) ;
\draw[->] (Solver) edge node [right] { (1b) } (Deploy) ; 385 398 \draw[->] (Solver) edge node [right] { (1b) } (Deploy) ;
\draw[->] (TCL) edge node [left] { (2) } (Bitstream) ; 386 399 \draw[->] (TCL) edge node [left] { (2) } (Bitstream) ;
\draw[->,dashed] (Bitstream) -- (Deploy) ; 387 400 \draw[->,dashed] (Bitstream) -- (Deploy) ;
\draw[->] (Deploy) to[out=-30,in=120] node [above] { (3) } (Board) ; 388 401 \draw[->] (Deploy) to[out=-30,in=120] node [above] { (3) } (Board) ;
\draw[->] (Board) to[out=150,in=-60] node [below] { (4) } (Deploy) ; 389 402 \draw[->] (Board) to[out=150,in=-60] node [below] { (4) } (Deploy) ;
\draw[->] (Deploy) edge node [left] { (5) } (Postproc) ; 390 403 \draw[->] (Deploy) edge node [left] { (5) } (Postproc) ;
\draw[->] (Postproc) -- (Results) ; 391 404 \draw[->] (Postproc) -- (Results) ;
\end{tikzpicture} 392 405 \end{tikzpicture}
\caption{Design workflow from the input parameters to the results} 393 406 \caption{Design workflow from the input parameters to the results}
\label{fig:workflow} 394 407 \label{fig:workflow}
\end{figure} 395 408 \end{figure}
396 409
The filter solver is a C++ program that takes as input the maximum area 397 410 The filter solver is a C++ program that takes as input the maximum area
$\mathcal{A}$, the number of stages $n$, the size of the input signal $\Pi^I$, 398 411 $\mathcal{A}$, the number of stages $n$, the size of the input signal $\Pi^I$,
the FIR configurations $(C_{ij}, \pi_{ij}^C)$ and the function $F$. It creates 399 412 the FIR configurations $(C_{ij}, \pi_{ij}^C)$ and the function $F$. It creates
the quadratic programs and uses the Gurobi solver to get the optimal results. 400 413 the quadratic programs and uses the Gurobi solver to get the optimal results.
Then it produces two scripts: a TCL script ((1a) on figure~\ref{fig:workflow}) 401 414 Then it produces two scripts: a TCL script ((1a) on figure~\ref{fig:workflow})
and a deploy script ((1b) on figure~\ref{fig:workflow}). 402 415 and a deploy script ((1b) on figure~\ref{fig:workflow}).
403 416
The TCL script describes the whole digital processing chain from the beginning 404 417 The TCL script describes the whole digital processing chain from the beginning
(the raw signal data) to the end (the filtered data). 405 418 (the raw signal data) to the end (the filtered data).
The raw input data generated from a Pseudo Random Number (PRN) 406 419 The raw input data generated from a Pseudo Random Number (PRN)
generator inside the FPGA and $\Pi^I$ is fixed at 16~bits. 407 420 generator inside the FPGA and $\Pi^I$ is fixed at 16~bits.
Then the script builds each stage of the chain with a generic FIR task that 408 421 Then the script builds each stage of the chain with a generic FIR task that
comes from a skeleton library. The generic FIR is highly configurable 409 422 comes from a skeleton library. The generic FIR is highly configurable
with the number of coefficients and the size of the coefficients. The coefficients 410 423 with the number of coefficients and the size of the coefficients. The coefficients
themselves are not stored in the script. 411 424 themselves are not stored in the script.
Whereas the signal is processed in real-time, the output signal is stored as 412 425 Whereas the signal is processed in real-time, the output signal is stored as
consecutive bursts of data. 413 426 consecutive bursts of data.
414 427
The TCL script is used by Vivado to produce the FPGA bitstream ((2) on figure~\ref{fig:workflow}). 415 428 The TCL script is used by Vivado to produce the FPGA bitstream ((2) on figure~\ref{fig:workflow}).
We use the 2018.2 version of Xilinx Vivado and we execute the synthesized 416 429 We use the 2018.2 version of Xilinx Vivado and we execute the synthesized
bitstream on a Redpitaya board fitted with a Xilinx Zynq-7010 series 417 430 bitstream on a Redpitaya board fitted with a Xilinx Zynq-7010 series
FPGA (xc7z010clg400-1) and two 125~MS/s ADC. 418 431 FPGA (xc7z010clg400-1) and two 125~MS/s ADC.
The board works with a Buildroot Linux image. We have developed some tools and 419 432 The board works with a Buildroot Linux image. We have developed some tools and
drivers to flash and communicate with the FPGA. They are used to automatize all 420 433 drivers to flash and communicate with the FPGA. They are used to automatize all
the workflow inside the board: load the filter coefficients and retrieve the 421 434 the workflow inside the board: load the filter coefficients and retrieve the
computed data. 422 435 computed data.
423 436
The deploy script uploads the bitstream to the board ((3) on 424 437 The deploy script uploads the bitstream to the board ((3) on
figure~\ref{fig:workflow}), flashes the FPGA, loads the different drivers, 425 438 figure~\ref{fig:workflow}), flashes the FPGA, loads the different drivers,
configures the coefficients of the FIR filters. It then waits for the results 426 439 configures the coefficients of the FIR filters. It then waits for the results
and retrieves the data to the main computer ((4) on figure~\ref{fig:workflow}). 427 440 and retrieves the data to the main computer ((4) on figure~\ref{fig:workflow}).
428 441
Finally, an Octave post-processing script computes the final results thanks to 429 442 Finally, an Octave post-processing script computes the final results thanks to
the output data ((5) on figure~\ref{fig:workflow}). 430 443 the output data ((5) on figure~\ref{fig:workflow}).
The results are normalized so that the Power Spectrum Density (PSD) starts at zero 431 444 The results are normalized so that the Power Spectrum Density (PSD) starts at zero
and the different configurations can be compared. 432 445 and the different configurations can be compared.
433 446
The workflow used to compute the results in section~\ref{sec:fixed_rej}, we 434 447 The workflow used to compute the results in section~\ref{sec:fixed_rej}, we
have just adapted the quadratic program but the rest of the workflow is unchanged. 435 448 have just adapted the quadratic program but the rest of the workflow is unchanged.
436 449
\section{Experiments with fixed area space} 437 450 \section{Experiments with fixed area space}
\label{sec:fixed_area} 438 451 \label{sec:fixed_area}
This section presents the output of the filter solver {\em i.e.} the computed 439 452 This section presents the output of the filter solver {\em i.e.} the computed
configurations for each stage, the computed rejection and the computed silicon area. 440 453 configurations for each stage, the computed rejection and the computed silicon area.
This is interesting to understand the choices made by the solver to compute its solutions. 441 454 This is interesting to understand the choices made by the solver to compute its solutions.
442 455
The experimental setup is composed of three cases. The raw input is generated 443 456 The experimental setup is composed of three cases. The raw input is generated
by a Pseudo Random Number (PRN) generator, which fixes the input data size $\Pi^I$. 444 457 by a Pseudo Random Number (PRN) generator, which fixes the input data size $\Pi^I$.
Then the total silicon area $\mathcal{A}$ has been fixed to either 500, 1000 or 1500 445 458 Then the total silicon area $\mathcal{A}$ has been fixed to either 500, 1000 or 1500
arbitrary units. Hence, the three cases have been named: MAX/500, MAX/1000, MAX/1500. 446 459 arbitrary units. Hence, the three cases have been named: MAX/500, MAX/1000, MAX/1500.
The number of configurations $p$ is 1827, with $C_i$ ranging from 3 to 60 and $\pi^C$ 447 460 The number of configurations $p$ is 1827, with $C_i$ ranging from 3 to 60 and $\pi^C$
ranging from 2 to 22. In each case, the quadratic program has been able to give a 448 461 ranging from 2 to 22. In each case, the quadratic program has been able to give a
result up to five stages ($n = 5$) in the cascaded filter. 449 462 result up to five stages ($n = 5$) in the cascaded filter.
450 463
Table~\ref{tbl:gurobi_max_500} shows the results obtained by the filter solver for MAX/500. 451 464 Table~\ref{tbl:gurobi_max_500} shows the results obtained by the filter solver for MAX/500.
Table~\ref{tbl:gurobi_max_1000} shows the results obtained by the filter solver for MAX/1000. 452 465 Table~\ref{tbl:gurobi_max_1000} shows the results obtained by the filter solver for MAX/1000.
Table~\ref{tbl:gurobi_max_1500} shows the results obtained by the filter solver for MAX/1500. 453 466 Table~\ref{tbl:gurobi_max_1500} shows the results obtained by the filter solver for MAX/1500.
454 467
\renewcommand{\arraystretch}{1.4} 455 468 \renewcommand{\arraystretch}{1.4}
456 469
\begin{table} 457 470 \begin{table}
\caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/500} 458 471 \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/500}
\label{tbl:gurobi_max_500} 459 472 \label{tbl:gurobi_max_500}
\centering 460 473 \centering
{\scalefont{0.77} 461 474 {\scalefont{0.77}
\begin{tabular}{|c|ccccc|c|c|} 462 475 \begin{tabular}{|c|ccccc|c|c|}
\hline 463 476 \hline
$n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ 464 477 $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\
\hline 465 478 \hline
1 & (21, 7, 0) & - & - & - & - & 32~dB & 483 \\ 466 479 1 & (21, 7, 0) & - & - & - & - & 32~dB & 483 \\
2 & (3, 3, 15) & (31, 9, 0) & - & - & - & 58~dB & 460 \\ 467 480 2 & (3, 3, 15) & (31, 9, 0) & - & - & - & 58~dB & 460 \\
3 & (3, 3, 15) & (27, 9, 0) & (5, 3, 0) & - & - & 66~dB & 488 \\ 468 481 3 & (3, 3, 15) & (27, 9, 0) & (5, 3, 0) & - & - & 66~dB & 488 \\
4 & (3, 3, 15) & (19, 7, 0) & (11, 5, 0) & (3, 3, 0) & - & 74~dB & 499 \\ 469 482 4 & (3, 3, 15) & (19, 7, 0) & (11, 5, 0) & (3, 3, 0) & - & 74~dB & 499 \\
5 & (3, 3, 15) & (23, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 78~dB & 489 \\ 470 483 5 & (3, 3, 15) & (23, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 78~dB & 489 \\
\hline 471 484 \hline
\end{tabular} 472 485 \end{tabular}
} 473 486 }
\end{table} 474 487 \end{table}
475 488
\begin{table} 476 489 \begin{table}
\caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1000} 477 490 \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1000}
\label{tbl:gurobi_max_1000} 478 491 \label{tbl:gurobi_max_1000}
\centering 479 492 \centering
{\scalefont{0.77} 480 493 {\scalefont{0.77}
\begin{tabular}{|c|ccccc|c|c|} 481 494 \begin{tabular}{|c|ccccc|c|c|}
\hline 482 495 \hline
$n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ 483 496 $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\
\hline 484 497 \hline
1 & (37, 11, 0) & - & - & - & - & 56~dB & 999 \\ 485 498 1 & (37, 11, 0) & - & - & - & - & 56~dB & 999 \\
2 & (3, 3, 15) & (51, 14, 0) & - & - & - & 87~dB & 975 \\ 486 499 2 & (3, 3, 15) & (51, 14, 0) & - & - & - & 87~dB & 975 \\
3 & (3, 3, 15) & (35, 11, 0) & (19, 7, 0) & - & - & 99~dB & 1000 \\ 487 500 3 & (3, 3, 15) & (35, 11, 0) & (19, 7, 0) & - & - & 99~dB & 1000 \\
4 & (3, 4, 16) & (27, 8, 0) & (19, 7, 1) & (11, 5, 0) & - & 103~dB & 998 \\ 488 501 4 & (3, 4, 16) & (27, 8, 0) & (19, 7, 1) & (11, 5, 0) & - & 103~dB & 998 \\
5 & (3, 3, 15) & (31, 9, 0) & (19, 7, 0) & (3, 3, 1) & (3, 3, 0) & 111~dB & 984 \\ 489 502 5 & (3, 3, 15) & (31, 9, 0) & (19, 7, 0) & (3, 3, 1) & (3, 3, 0) & 111~dB & 984 \\
\hline 490 503 \hline
\end{tabular} 491 504 \end{tabular}
} 492 505 }
\end{table} 493 506 \end{table}
494 507
\begin{table} 495 508 \begin{table}
\caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1500} 496 509 \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1500}
\label{tbl:gurobi_max_1500} 497 510 \label{tbl:gurobi_max_1500}
\centering 498 511 \centering
{\scalefont{0.77} 499 512 {\scalefont{0.77}
\begin{tabular}{|c|ccccc|c|c|} 500 513 \begin{tabular}{|c|ccccc|c|c|}
\hline 501 514 \hline
$n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ 502 515 $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\
\hline 503 516 \hline
1 & (47, 15, 0) & - & - & - & - & 71~dB & 1457 \\ 504 517 1 & (47, 15, 0) & - & - & - & - & 71~dB & 1457 \\
2 & (19, 6, 15) & (51, 14, 0) & - & - & - & 103~dB & 1489 \\ 505 518 2 & (19, 6, 15) & (51, 14, 0) & - & - & - & 103~dB & 1489 \\
3 & (3, 3, 15) & (35, 11, 0) & (35, 11, 0) & - & - & 122~dB & 1492 \\ 506 519 3 & (3, 3, 15) & (35, 11, 0) & (35, 11, 0) & - & - & 122~dB & 1492 \\
4 & (3, 3, 15) & (27, 8, 0) & (19, 7, 0) & (27, 9, 0) & - & 129~dB & 1498 \\ 507 520 4 & (3, 3, 15) & (27, 8, 0) & (19, 7, 0) & (27, 9, 0) & - & 129~dB & 1498 \\
5 & (3, 3, 15) & (23, 9, 2) & (27, 9, 0) & (19, 7, 0) & (3, 3, 0) & 136~dB & 1499 \\ 508 521 5 & (3, 3, 15) & (23, 9, 2) & (27, 9, 0) & (19, 7, 0) & (3, 3, 0) & 136~dB & 1499 \\
\hline 509 522 \hline
\end{tabular} 510 523 \end{tabular}
} 511 524 }
\end{table} 512 525 \end{table}
513 526
\renewcommand{\arraystretch}{1} 514 527 \renewcommand{\arraystretch}{1}
515 528
From these tables, we can first state that the more stages are used to define 516 529 From these tables, we can first state that the more stages are used to define
the cascaded FIR filters, the better the rejection. It was an expected result as it has 517 530 the cascaded FIR filters, the better the rejection. It was an expected result as it has
been previously observed that many small filters are better than 518 531 been previously observed that many small filters are better than
a single large filter \cite{lim_1988, lim_1996, young_1992}, despite such conclusion 519 532 a single large filter \cite{lim_1988, lim_1996, young_1992}, despite such conclusion
being hardly used in practice due to the lack of tools for identifying individual filter 520 533 being hardly used in practice due to the lack of tools for identifying individual filter
coefficients in the cascaded approach. 521 534 coefficients in the cascaded approach.
522 535
Second, the larger the silicon area, the better the rejection. This was also an 523 536 Second, the larger the silicon area, the better the rejection. This was also an
expected result as more area means a filter of better quality (more coefficients 524 537 expected result as more area means a filter of better quality (more coefficients
or more bits per coefficient). 525 538 or more bits per coefficient).
526 539
Then, we also observe that the first stage can have a larger shift than the other 527 540 Then, we also observe that the first stage can have a larger shift than the other
stages. This is explained by the fact that the solver tries to use just enough 528 541 stages. This is explained by the fact that the solver tries to use just enough
bits for the computed rejection after each stage. In the first stage, a 529 542 bits for the computed rejection after each stage. In the first stage, a
balance between a strong rejection with a low number of bits is targeted. Equation~\ref{eq:maxshift} 530 543 balance between a strong rejection with a low number of bits is targeted. Equation~\ref{eq:maxshift}
gives the relation between both values. 531 544 gives the relation between both values.
532 545
Finally, we note that the solver consumes all the given silicon area. 533 546 Finally, we note that the solver consumes all the given silicon area.
534 547
The following graphs present the rejection for real data on the FPGA. In all following 535 548 The following graphs present the rejection for real data on the FPGA. In all following
figures, the solid line represents the actual rejection of the filtered 536 549 figures, the solid line represents the actual rejection of the filtered
data on the FPGA as measured experimentally and the dashed line are the noise level 537 550 data on the FPGA as measured experimentally and the dashed line are the noise level
given by the quadratic solver. The configurations are those computed in the previous section. 538 551 given by the quadratic solver. The configurations are those computed in the previous section.
539 552
Figure~\ref{fig:max_500_result} shows the rejection of the different configurations in the case of MAX/500. 540 553 Figure~\ref{fig:max_500_result} shows the rejection of the different configurations in the case of MAX/500.
Figure~\ref{fig:max_1000_result} shows the rejection of the different configurations in the case of MAX/1000. 541 554 Figure~\ref{fig:max_1000_result} shows the rejection of the different configurations in the case of MAX/1000.
Figure~\ref{fig:max_1500_result} shows the rejection of the different configurations in the case of MAX/1500. 542 555 Figure~\ref{fig:max_1500_result} shows the rejection of the different configurations in the case of MAX/1500.
543 556
\begin{figure} 544 557 \begin{figure}
\centering 545 558 \centering
\includegraphics[width=\linewidth]{images/max_500} 546 559 \includegraphics[width=\linewidth]{images/max_500}
\caption{Signal spectrum for MAX/500} 547 560 \caption{Signal spectrum for MAX/500}
\label{fig:max_500_result} 548 561 \label{fig:max_500_result}
\end{figure} 549 562 \end{figure}
550 563
\begin{figure} 551 564 \begin{figure}
\centering 552 565 \centering
\includegraphics[width=\linewidth]{images/max_1000} 553 566 \includegraphics[width=\linewidth]{images/max_1000}
\caption{Signal spectrum for MAX/1000} 554 567 \caption{Signal spectrum for MAX/1000}
\label{fig:max_1000_result} 555 568 \label{fig:max_1000_result}
\end{figure} 556 569 \end{figure}
557 570
\begin{figure} 558 571 \begin{figure}
\centering 559 572 \centering
\includegraphics[width=\linewidth]{images/max_1500} 560 573 \includegraphics[width=\linewidth]{images/max_1500}
\caption{Signal spectrum for MAX/1500} 561 574 \caption{Signal spectrum for MAX/1500}
\label{fig:max_1500_result} 562 575 \label{fig:max_1500_result}
\end{figure} 563 576 \end{figure}
564 577
In all cases, we observe that the actual rejection is close to the rejection computed by the solver. 565 578 In all cases, we observe that the actual rejection is close to the rejection computed by the solver.
566 579
We compare the actual silicon resources given by Vivado to the 567 580 We compare the actual silicon resources given by Vivado to the
resources in arbitrary units. 568 581 resources in arbitrary units.
The goal is to check that our arbitrary units of silicon area models well enough 569 582 The goal is to check that our arbitrary units of silicon area models well enough
the real resources on the FPGA. Especially we want to verify that, for a given 570 583 the real resources on the FPGA. Especially we want to verify that, for a given
number of arbitrary units, the actual silicon resources do not depend on the 571 584 number of arbitrary units, the actual silicon resources do not depend on the
number of stages $n$. Most significantly, our approach aims 572 585 number of stages $n$. Most significantly, our approach aims
at remaining far enough from the practical logic gate implementation used by 573 586 at remaining far enough from the practical logic gate implementation used by
various vendors to remain platform independent and be portable from one 574 587 various vendors to remain platform independent and be portable from one
architecture to another. 575 588 architecture to another.
576 589
Table~\ref{tbl:resources_usage} shows the resources usage in the case of MAX/500, MAX/1000 and 577 590 Table~\ref{tbl:resources_usage} shows the resources usage in the case of MAX/500, MAX/1000 and
MAX/1500 \emph{i.e.} when the maximum allowed silicon area is fixed to 500, 1000 578 591 MAX/1500 \emph{i.e.} when the maximum allowed silicon area is fixed to 500, 1000
and 1500 arbitrary units. We have taken care to extract solely the resources used by 579 592 and 1500 arbitrary units. We have taken care to extract solely the resources used by
the FIR filters and remove additional processing blocks including FIFO and PL to 580 593 the FIR filters and remove additional processing blocks including FIFO and PL to
PS communication. 581 594 PS communication.
582 595
\begin{table} 583 596 \begin{table}
\caption{Resource occupation. The last column refers to available resources on a Zynq-7010 as found on the Redpitaya.} 584 597 \caption{Resource occupation. The last column refers to available resources on a Zynq-7010 as found on the Redpitaya.}
\label{tbl:resources_usage} 585 598 \label{tbl:resources_usage}
\centering 586 599 \centering
\begin{tabular}{|c|c|ccc|c|} 587 600 \begin{tabular}{|c|c|ccc|c|}
\hline 588 601 \hline
$n$ & & MAX/500 & MAX/1000 & MAX/1500 & \emph{Zynq 7010} \\ \hline\hline 589 602 $n$ & & MAX/500 & MAX/1000 & MAX/1500 & \emph{Zynq 7010} \\ \hline\hline
& LUT & 249 & 453 & 627 & \emph{17600} \\ 590 603 & LUT & 249 & 453 & 627 & \emph{17600} \\
1 & BRAM & 1 & 1 & 1 & \emph{120} \\ 591 604 1 & BRAM & 1 & 1 & 1 & \emph{120} \\
& DSP & 21 & 37 & 47 & \emph{80} \\ \hline 592 605 & DSP & 21 & 37 & 47 & \emph{80} \\ \hline
& LUT & 2374 & 5494 & 691 & \emph{17600} \\ 593 606 & LUT & 2374 & 5494 & 691 & \emph{17600} \\
2 & BRAM & 2 & 2 & 2 & \emph{120} \\ 594 607 2 & BRAM & 2 & 2 & 2 & \emph{120} \\
& DSP & 0 & 0 & 70 & \emph{80} \\ \hline 595 608 & DSP & 0 & 0 & 70 & \emph{80} \\ \hline
& LUT & 2443 & 3304 & 3521 & \emph{17600} \\ 596 609 & LUT & 2443 & 3304 & 3521 & \emph{17600} \\
3 & BRAM & 3 & 3 & 3 & \emph{120} \\ 597 610 3 & BRAM & 3 & 3 & 3 & \emph{120} \\
& DSP & 0 & 19 & 35 & \emph{80} \\ \hline 598 611 & DSP & 0 & 19 & 35 & \emph{80} \\ \hline
& LUT & 2634 & 3753 & 2557 & \emph{17600} \\ 599 612 & LUT & 2634 & 3753 & 2557 & \emph{17600} \\
4 & BRAM & 4 & 4 & 4 & \emph{120} \\ 600 613 4 & BRAM & 4 & 4 & 4 & \emph{120} \\
& DPS & 0 & 19 & 46 & \emph{80} \\ \hline 601 614 & DPS & 0 & 19 & 46 & \emph{80} \\ \hline
& LUT & 2423 & 3047 & 2847 & \emph{17600} \\ 602 615 & LUT & 2423 & 3047 & 2847 & \emph{17600} \\
5 & BRAM & 5 & 5 & 5 & \emph{120} \\ 603 616 5 & BRAM & 5 & 5 & 5 & \emph{120} \\
& DPS & 0 & 22 & 46 & \emph{80} \\ \hline 604 617 & DPS & 0 & 22 & 46 & \emph{80} \\ \hline
\end{tabular} 605 618 \end{tabular}
\end{table} 606 619 \end{table}
607 620
In some cases, Vivado replaces the DSPs by Look Up Tables (LUTs). We assume that, 608 621 In some cases, Vivado replaces the DSPs by Look Up Tables (LUTs). We assume that,
when the filters coefficients are small enough, or when the input size is small 609 622 when the filters coefficients are small enough, or when the input size is small
enough, Vivado optimized resource consumption by selecting multiplexers to 610 623 enough, Vivado optimized resource consumption by selecting multiplexers to
implement the multiplications instead of a DSP. In this case, it is quite difficult 611 624 implement the multiplications instead of a DSP. In this case, it is quite difficult
to compare the whole silicon budget. 612 625 to compare the whole silicon budget.
613 626
However, a rough estimation can be made with a simple equivalence. Looking at 614 627 However, a rough estimation can be made with a simple equivalence. Looking at
the first column (MAX/500), where the number of LUTs is quite stable for $n \geq 2$, 615 628 the first column (MAX/500), where the number of LUTs is quite stable for $n \geq 2$,
we can deduce that a DSP is roughly equivalent to 100~LUTs in terms of silicon 616 629 we can deduce that a DSP is roughly equivalent to 100~LUTs in terms of silicon
area use. With this equivalence, our 500 arbitraty units corresponds to 2500 LUTs, 617 630 area use. With this equivalence, our 500 arbitraty units corresponds to 2500 LUTs,
1000 arbitrary units corresponds to 5000 LUTs and 1500 arbitrary units corresponds 618 631 1000 arbitrary units corresponds to 5000 LUTs and 1500 arbitrary units corresponds
to 7300 LUTs. The conclusion is that the orders of magnitude of our arbitrary 619 632 to 7300 LUTs. The conclusion is that the orders of magnitude of our arbitrary
unit are quite good. The relatively small differences can probably be explained 620 633 unit are quite good. The relatively small differences can probably be explained
by the optimizations done by Vivado based on the detailed map of available processing resources. 621 634 by the optimizations done by Vivado based on the detailed map of available processing resources.
622 635
We present the computation time to solve the quadratic problem. 623 636 We present the computation time to solve the quadratic problem.
For each case, the filter solver software are executed with a Intel(R) Xeon(R) CPU E5606 624 637 For each case, the filter solver software are executed with a Intel(R) Xeon(R) CPU E5606
cadenced at 2.13~GHz. The CPU has 8 cores that are used by Gurobi to solve 625 638 cadenced at 2.13~GHz. The CPU has 8 cores that are used by Gurobi to solve
the quadratic problem. 626 639 the quadratic problem.
627 640
Table~\ref{tbl:area_time} shows the time needed to solve the quadratic 628 641 Table~\ref{tbl:area_time} shows the time needed to solve the quadratic
problem when the maximal area is fixed to 500, 1000 and 1500 arbitrary units. 629 642 problem when the maximal area is fixed to 500, 1000 and 1500 arbitrary units.
630 643
\begin{table} 631 644 \begin{table}
\caption{Time to solve the quadratic program with Gurobi} 632 645 \caption{Time to solve the quadratic program with Gurobi}
\label{tbl:area_time} 633 646 \label{tbl:area_time}
\centering 634 647 \centering
\begin{tabular}{|c|c|c|c|}\hline 635 648 \begin{tabular}{|c|c|c|c|}\hline
$n$ & Time (MAX/500) & Time (MAX/1000) & Time (MAX/1500) \\\hline\hline 636 649 $n$ & Time (MAX/500) & Time (MAX/1000) & Time (MAX/1500) \\\hline\hline
1 & 0.1~s & 0.1~s & 0.3~s \\ 637 650 1 & 0.1~s & 0.1~s & 0.3~s \\
2 & 1.1~s & 2.2~s & 12~s \\ 638 651 2 & 1.1~s & 2.2~s & 12~s \\
3 & 17~s & 137~s ($\approx$ 2~min) & 275~s ($\approx$ 4~min) \\ 639 652 3 & 17~s & 137~s ($\approx$ 2~min) & 275~s ($\approx$ 4~min) \\
4 & 52~s & 5448~s ($\approx$ 90~min) & 5505~s ($\approx$ 17~h) \\ 640 653 4 & 52~s & 5448~s ($\approx$ 90~min) & 5505~s ($\approx$ 17~h) \\
5 & 286~s ($\approx$ 4~min) & 4119~s ($\approx$ 68~min) & 235479~s ($\approx$ 3~days) \\\hline 641 654 5 & 286~s ($\approx$ 4~min) & 4119~s ($\approx$ 68~min) & 235479~s ($\approx$ 3~days) \\\hline
\end{tabular} 642 655 \end{tabular}
\end{table} 643 656 \end{table}
644 657
As expected, the computation time seems to rise exponentially with the number of stages. % TODO: exponentiel ? 645 658 As expected, the computation time seems to rise exponentially with the number of stages. % TODO: exponentiel ?
When the area is limited, the design exploration space is more limited and the solver is able to 646 659 When the area is limited, the design exploration space is more limited and the solver is able to
find an optimal solution faster. On the contrary, in the case of MAX/1500 with 647 660 find an optimal solution faster. On the contrary, in the case of MAX/1500 with
5~stages, we were not able to obtain a result after 40~hours of computation so we decided to stop. 648 661 5~stages, we were not able to obtain a result after 40~hours of computation so we decided to stop.
649 662
\section{Experiments with fixed rejection target} 650 663 \section{Experiments with fixed rejection target}
\label{sec:fixed_rej} 651 664 \label{sec:fixed_rej}
This section presents the results of complementary quadratic program which we 652 665 This section presents the results of complementary quadratic program which we
minimize the area occupation for a targeted noise level. 653 666 minimize the area occupation for a targeted noise level.
654 667
The experimental setup is also composed of three cases. The raw input is the same 655 668 The experimental setup is also composed of three cases. The raw input is the same
as previous section, a PRN generator, which fixes the input data size $\Pi^I$. 656 669 as previous section, a PRN generator, which fixes the input data size $\Pi^I$.
Then the targeted rejection $\mathcal{R}$ has been fixed to either 40, 60 or 80~dB. 657 670 Then the targeted rejection $\mathcal{R}$ has been fixed to either 40, 60 or 80~dB.
Hence, the three cases have been named: MIN/40, MIN/60, MIN/80. 658 671 Hence, the three cases have been named: MIN/40, MIN/60, MIN/80.
The number of configurations $p$ is the same as previous section. 659 672 The number of configurations $p$ is the same as previous section.
660 673
Table~\ref{tbl:gurobi_min_40} shows the results obtained by the filter solver for MIN/40. 661 674 Table~\ref{tbl:gurobi_min_40} shows the results obtained by the filter solver for MIN/40.
Table~\ref{tbl:gurobi_min_60} shows the results obtained by the filter solver for MIN/60. 662 675 Table~\ref{tbl:gurobi_min_60} shows the results obtained by the filter solver for MIN/60.
Table~\ref{tbl:gurobi_min_80} shows the results obtained by the filter solver for MIN/80. 663 676 Table~\ref{tbl:gurobi_min_80} shows the results obtained by the filter solver for MIN/80.
664 677
\renewcommand{\arraystretch}{1.4} 665 678 \renewcommand{\arraystretch}{1.4}
666 679
\begin{table} 667 680 \begin{table}
\caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/40} 668 681 \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/40}
\label{tbl:gurobi_min_40} 669 682 \label{tbl:gurobi_min_40}
\centering 670 683 \centering
{\scalefont{0.77} 671 684 {\scalefont{0.77}
\begin{tabular}{|c|ccccc|c|c|} 672 685 \begin{tabular}{|c|ccccc|c|c|}
\hline 673 686 \hline
$n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ 674 687 $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\
\hline 675 688 \hline
1 & (27, 8, 0) & - & - & - & - & 41~dB & 648 \\ 676 689 1 & (27, 8, 0) & - & - & - & - & 41~dB & 648 \\
2 & (3, 2, 14) & (19, 7, 0) & - & - & - & 40~dB & 263 \\ 677 690 2 & (3, 2, 14) & (19, 7, 0) & - & - & - & 40~dB & 263 \\
3 & (3, 3, 15) & (11, 5, 0) & (3, 3, 0) & - & - & 41~dB & 192 \\ 678 691 3 & (3, 3, 15) & (11, 5, 0) & (3, 3, 0) & - & - & 41~dB & 192 \\
4 & (3, 3, 15) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & - & 42~dB & 147 \\ 679 692 4 & (3, 3, 15) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & - & 42~dB & 147 \\
\hline 680 693 \hline
\end{tabular} 681 694 \end{tabular}
} 682 695 }
\end{table} 683 696 \end{table}
684 697
\begin{table} 685 698 \begin{table}
\caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/60} 686 699 \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/60}
\label{tbl:gurobi_min_60} 687 700 \label{tbl:gurobi_min_60}
\centering 688 701 \centering
{\scalefont{0.77} 689 702 {\scalefont{0.77}
\begin{tabular}{|c|ccccc|c|c|} 690 703 \begin{tabular}{|c|ccccc|c|c|}
\hline 691 704 \hline
$n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ 692 705 $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\
\hline 693 706 \hline
1 & (39, 13, 0) & - & - & - & - & 60~dB & 1131 \\ 694 707 1 & (39, 13, 0) & - & - & - & - & 60~dB & 1131 \\
2 & (3, 3, 15) & (35, 10, 0) & - & - & - & 60~dB & 547 \\ 695 708 2 & (3, 3, 15) & (35, 10, 0) & - & - & - & 60~dB & 547 \\
3 & (3, 3, 15) & (27, 8, 0) & (3, 3, 0) & - & - & 62~dB & 426 \\ 696 709 3 & (3, 3, 15) & (27, 8, 0) & (3, 3, 0) & - & - & 62~dB & 426 \\
4 & (3, 2, 14) & (11, 5, 1) & (11, 5, 0) & (3, 3, 0) & - & 60~dB & 344 \\ 697 710 4 & (3, 2, 14) & (11, 5, 1) & (11, 5, 0) & (3, 3, 0) & - & 60~dB & 344 \\
5 & (3, 2, 14) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & 60~dB & 279 \\ 698 711 5 & (3, 2, 14) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & 60~dB & 279 \\
\hline 699 712 \hline
\end{tabular} 700 713 \end{tabular}
} 701 714 }
\end{table} 702 715 \end{table}
703 716
\begin{table} 704 717 \begin{table}
\caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/80} 705 718 \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/80}
\label{tbl:gurobi_min_80} 706 719 \label{tbl:gurobi_min_80}
\centering 707 720 \centering
{\scalefont{0.77} 708 721 {\scalefont{0.77}
\begin{tabular}{|c|ccccc|c|c|} 709 722 \begin{tabular}{|c|ccccc|c|c|}
\hline 710 723 \hline
$n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ 711 724 $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\
\hline 712 725 \hline
1 & (55, 16, 0) & - & - & - & - & 81~dB & 1760 \\ 713 726 1 & (55, 16, 0) & - & - & - & - & 81~dB & 1760 \\
2 & (3, 3, 15) & (47, 14, 0) & - & - & - & 80~dB & 903 \\ 714 727 2 & (3, 3, 15) & (47, 14, 0) & - & - & - & 80~dB & 903 \\
3 & (3, 3, 15) & (23, 9, 0) & (19, 7, 0) & - & - & 80~dB & 698 \\ 715 728 3 & (3, 3, 15) & (23, 9, 0) & (19, 7, 0) & - & - & 80~dB & 698 \\
4 & (3, 3, 15) & (27, 9, 0) & (7, 7, 4) & (3, 3, 0) & - & 80~dB & 605 \\ 716 729 4 & (3, 3, 15) & (27, 9, 0) & (7, 7, 4) & (3, 3, 0) & - & 80~dB & 605 \\
5 & (3, 2, 14) & (27, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 81~dB & 534 \\ 717 730 5 & (3, 2, 14) & (27, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 81~dB & 534 \\
\hline 718 731 \hline
\end{tabular} 719 732 \end{tabular}
} 720 733 }
\end{table} 721 734 \end{table}
\renewcommand{\arraystretch}{1} 722 735 \renewcommand{\arraystretch}{1}
723 736
From these tables, we can first state that all configuration reach the target rejection 724 737 From these tables, we can first state that all configuration reach the target rejection
level and more we have stages lesser is the area occupied in arbitrary unit. 725 738 level and more we have stages lesser is the area occupied in arbitrary unit.
Futhermore, the area of the monolithic filter is twice bigger than the two cascaded. 726 739 Futhermore, the area of the monolithic filter is twice bigger than the two cascaded.
More generally, more there is filters lower is the occupied area. 727 740 More generally, more there is filters lower is the occupied area.
728 741
Like in previous section, the solver choose always a little filter as first 729 742 Like in previous section, the solver choose always a little filter as first
filter stage and the second one is often the biggest filter. this choice can be explain 730 743 filter stage and the second one is often the biggest filter. this choice can be explain
as the previous section. The solver uses just enough bits to not degrade the input 731 744 as the previous section. The solver uses just enough bits to not degrade the input
signal and in second filter it can choose a better filter to improve rejection without 732 745 signal and in second filter it can choose a better filter to improve rejection without
have too bits in the output data. 733 746 have too bits in the output data.
734 747
For the specific case in MIN/40 for $n = 5$ the solver has determined that the optimal 735 748 For the specific case in MIN/40 for $n = 5$ the solver has determined that the optimal
number of filter is 4 so it not chose any configuration in last filter. Hence this 736 749 number of filter is 4 so it not chose any configuration in last filter. Hence this
solution is equivalent to the result for $n = 4$. 737 750 solution is equivalent to the result for $n = 4$.
738 751
The following graphs present the rejection for real data on the FPGA. In all following 739 752 The following graphs present the rejection for real data on the FPGA. In all following
figures, the solid line represents the actual rejection of the filtered 740 753 figures, the solid line represents the actual rejection of the filtered
data on the FPGA as measured experimentally and the dashed line are the noise level 741 754 data on the FPGA as measured experimentally and the dashed line are the noise level
given by the quadratic solver. 742 755 given by the quadratic solver.
743 756
Figure~\ref{fig:min_40} shows the rejection of the different configurations in the case of MIN/40. 744 757 Figure~\ref{fig:min_40} shows the rejection of the different configurations in the case of MIN/40.
Figure~\ref{fig:min_60} shows the rejection of the different configurations in the case of MIN/60. 745 758 Figure~\ref{fig:min_60} shows the rejection of the different configurations in the case of MIN/60.
Figure~\ref{fig:min_80} shows the rejection of the different configurations in the case of MIN/80. 746 759 Figure~\ref{fig:min_80} shows the rejection of the different configurations in the case of MIN/80.
747 760
\begin{figure} 748 761 \begin{figure}
\centering 749 762 \centering