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File was created 1 @thesis{gwen-cogen,
2 author = {Gwenhaël Goavec-Merou},
3 title = {Générateur de coprocesseur pour le traitement de données en flux (vidéo ou similaire) sur FPGA},
4 institution = {FEMTO-ST},
5 year = {2014}
6 }
7
8 @article{hide,
9 title={HIDE: A hardware intelligent description environment},
10 author={Benkrid, Khaled and Belkacemi, S and Benkrid, Abdsamad},
11 journal={Microprocessors and Microsystems},
12 volume={30},
13 number={6},
14 pages={283--300},
15 year={2006},
16 publisher={Elsevier}
17 }
18
19 @inproceedings{skeleton,
20 title={High level programming for FPGA based image and video processing using hardware skeletons},
21 author={Benkrid, Khaled and Crookes, Danny and Smith, J and Benkrid, Abdsamad},
22 booktitle={Field-Programmable Custom Computing Machines, 2001. FCCM'01. The 9th Annual IEEE Symposium on},
23 pages={219--226},
24 year={2001},
25 organization={IEEE}
26 }
27
28 @article{benkrid2004application,
29 title={From application descriptions to hardware in seconds: a logic-based approach to bridging the gap},
30 author={Benkrid, Khaled and Crookes, Danny},
31 journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on},
32 volume={12},
33 number={4},
34 pages={420--436},
35 year={2004},
36 publisher={IEEE}
37 }
38
39 @phdthesis{these-dsp-fpga,
40 title={Design methodologies and architectures for digital signal processing on FPGAs},
41 author={Mirzaei, Shahnam},
42 year={2010},
43 school={UNIVERSITY OF CALIFORNIA SANTA BARBARA}
44 }
45
46 @article{def1-ordo,
47 title={Algorithmique Parallèle-Cours Et Exercices Corrigés},
48 author={Legrand, Arnaud and Robert, Yves},
49 year={2003},
50 publisher={Dunod}
51 }
52
53 @article{these-mathias,
54 title={Optimisation du débit pour des applications linéaires multi-tâches sur plateformes distribuées incluant des temps de reconfiguration},
55 author={Coqblin, Mathias},
56 institution = {FEMTO-ST},
57 year={2012}
58 }
59
60 @thesis{these-alex,
61 author = {Alexandru Dobrila},
62 title = {Optimisation du débit en environnement distribué incertain},
63 institution = {FEMTO-ST},
64 year = {2011}
65 }
66
67 @book{def2-ordo,
68 title={Handbook of scheduling: algorithms, models, and performance analysis},
69 author={Leung, Joseph YT},
70 year={2004},
71 publisher={CRC Press}
72 }
73
74 @inproceedings{def-ordo-en-ligne,
75 title={On the Definition of "On-Line" in Job Scheduling Problems},
76 author={Feitelson, Dror G and Mu'alem, Ahuva W},
77 booktitle={SIGACT NEWS},
78 year={2000},
79 organization={Citeseer}
80 }
81
82 @article{shmueli2005backfilling,
83 title={Backfilling with lookahead to optimize the packing of parallel jobs},
84 author={Shmueli, Edi and Feitelson, Dror G},
85 journal={Journal of Parallel and Distributed Computing},
86 volume={65},
87 number={9},
88 pages={1090--1107},
89 year={2005},
90 publisher={Elsevier}
91 }
92
93 @article{graham1979optimization,
94 title={Optimization and approximation in deterministic sequencing and scheduling: a survey},
95 author={Graham, Ronald L and Lawler, Eugene L and Lenstra, Jan Karel and Kan, AHG Rinnooy},
96 journal={Annals of discrete mathematics},
97 volume={5},
98 pages={287--326},
99 year={1979},
100 publisher={Elsevier}
101 }
102
103 @article{salvador2012accelerating,
104 title={Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling},
105 author={Salvador, Ruben and Vidal, Alberto and Moreno, Felix and Riesgo, Teresa and Sekanina, Lukas},
106 journal={Microprocessors and Microsystems},
107 volume={36},
108 number={5},
109 pages={427--438},
110 year={2012},
111 publisher={Elsevier}
112 }
113
114 @article{zhuo2007scalable,
115 title={Scalable and modular algorithms for floating-point matrix multiplication on reconfigurable computing systems},
116 author={Zhuo, Ling and Prasanna, Viktor K},
117 journal={Parallel and Distributed Systems, IEEE Transactions on},
118 volume={18},
119 number={4},
120 pages={433--448},
121 year={2007},
122 publisher={IEEE}
123 }
124
125 @article{olariu1993computing,
126 title={Computing the Hough transform on reconfigurable meshes},
127 author={Olariu, Stephan and Schwing, James L and Zhang, Jingyuan},
128 journal={Image and vision computing},
129 volume={11},
130 number={10},
131 pages={623--628},
132 year={1993},
133 publisher={Elsevier}
134 }
135
136 @article{pan1999improved,
137 title={An improved constant-time algorithm for computing the Radon and Hough transforms on a reconfigurable mesh},
138 author={Pan, Yi and Li, Keqin and Hamdi, Mounir},
139 journal={Systems, Man and Cybernetics, Part A: Systems and Humans, IEEE Transactions on},
140 volume={29},
141 number={4},
142 pages={417--421},
143 year={1999},
144 publisher={IEEE}
145 }
146
147 @article{kasbah2008multigrid,
148 title={Multigrid solvers in reconfigurable hardware},
149 author={Kasbah, Safaa J and Damaj, Issam W and Haraty, Ramzi A},
150 journal={Journal of Computational and Applied Mathematics},
151 volume={213},
152 number={1},
153 pages={79--94},
154 year={2008},
155 publisher={Elsevier}
156 }
157
158 @inproceedings{crookes1998environment,
159 title={An environment for generating FPGA architectures for image algebra-based algorithms},
160 author={Crookes, Danny and Alotaibi, Khalid and Bouridane, Ahmed and Donachy, Paul and Benkrid, Abdsamad},
161 booktitle={Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on},
162 pages={990--994},
163 year={1998},
164 organization={IEEE}
165 }
166
167 @article{crookes2000design,
168 title={Design and implementation of a high level programming environment for FPGA-based image processing},
ifcs2018_proceeding.tex
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\documentclass[a4paper,conference]{IEEEtran/IEEEtran} 1 1 \documentclass[a4paper,conference]{IEEEtran/IEEEtran}
\usepackage{graphicx,color,hyperref} 2 2 \usepackage{graphicx,color,hyperref}
\usepackage{amsfonts} 3 3 \usepackage{amsfonts}
4 \usepackage{amsthm}
5 \usepackage{amssymb}
6 \usepackage{amsmath}
\usepackage{url} 4 7 \usepackage{url}
\usepackage[normalem]{ulem} 5 8 \usepackage[normalem]{ulem}
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% correct bad hyphenation here 7 10 % correct bad hyphenation here
\hyphenation{op-tical net-works semi-conduc-tor} 8 11 \hyphenation{op-tical net-works semi-conduc-tor}
\textheight=26cm 9 12 \textheight=26cm
\setlength{\footskip}{30pt} 10 13 \setlength{\footskip}{30pt}
\pagenumbering{gobble} 11 14 \pagenumbering{gobble}
\begin{document} 12 15 \begin{document}
\title{Filter optimization for real time digital processing of radiofrequency signals: application 13 16 \title{Filter optimization for real time digital processing of radiofrequency signals: application
to oscillator metrology} 14 17 to oscillator metrology}
15 18
\author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2}, 16 19 \author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2},
G. Goavec-M\'erou\IEEEauthorrefmark{1}, 17 20 G. Goavec-M\'erou\IEEEauthorrefmark{1},
P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}} 18 21 P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}}
\IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France } 19 22 \IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France }
\IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\ 20 23 \IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\
Email: \{pyb2,jmfriedt\}@femto-st.fr} 21 24 Email: \{pyb2,jmfriedt\}@femto-st.fr}
} 22 25 }
\maketitle 23 26 \maketitle
\thispagestyle{plain} 24 27 \thispagestyle{plain}
\pagestyle{plain} 25 28 \pagestyle{plain}
29 \newtheorem{definition}{Definition}
26 30
\begin{abstract} 27 31 \begin{abstract}
Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to 28 32 Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to
radiofrequency signal processing. Applied to oscillator characterization in the context 29 33 radiofrequency signal processing. Applied to oscillator characterization in the context
of ultrastable clocks, stringent filtering requirements are defined by spurious signal or 30 34 of ultrastable clocks, stringent filtering requirements are defined by spurious signal or
noise rejection needs. Since real time radiofrequency processing must be performed in a 31 35 noise rejection needs. Since real time radiofrequency processing must be performed in a
Field Programmable Array to meet timing constraints, we investigate optimization strategies 32 36 Field Programmable Array to meet timing constraints, we investigate optimization strategies
to design filters meeting rejection characteristics while limiting the hardware resources 33 37 to design filters meeting rejection characteristics while limiting the hardware resources
required and keeping timing constraints within the targeted measurement bandwidths. 34 38 required and keeping timing constraints within the targeted measurement bandwidths.
\end{abstract} 35 39 \end{abstract}
36 40
\begin{IEEEkeywords} 37 41 \begin{IEEEkeywords}
Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter 38 42 Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter
\end{IEEEkeywords} 39 43 \end{IEEEkeywords}
40 44
\section{Digital signal processing of ultrastable clock signals} 41 45 \section{Digital signal processing of ultrastable clock signals}
42 46
Analog oscillator phase noise characteristics are classically performed by downconverting 43 47 Analog oscillator phase noise characteristics are classically performed by downconverting
the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband, 44 48 the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband,
followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In 45 49 followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In
a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by 46 50 a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by
multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}. 47 51 multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}.
48 52
\begin{figure}[h!tb] 49 53 \begin{figure}[h!tb]
\begin{center} 50 54 \begin{center}
\includegraphics[width=.8\linewidth]{images/schema} 51 55 \includegraphics[width=.8\linewidth]{images/schema}
\end{center} 52 56 \end{center}
\caption{Fully digital oscillator phase noise characterization: the Device Under Test 53 57 \caption{Fully digital oscillator phase noise characterization: the Device Under Test
(DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and 54 58 (DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and
downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals 55 59 downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals
and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite 56 60 and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite
Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays 57 61 Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays
the spectral characteristics of the phase fluctuations.} 58 62 the spectral characteristics of the phase fluctuations.}
\label{schema} 59 63 \label{schema}
\end{figure} 60 64 \end{figure}
61 65
As with the analog mixer, 62 66 As with the analog mixer,
the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as 63 67 the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as
well as the generation of the frequency sum signal in addition to the frequency difference. 64 68 well as the generation of the frequency sum signal in addition to the frequency difference.
These unwanted spectral characteristics must be rejected before decimating the data stream 65 69 These unwanted spectral characteristics must be rejected before decimating the data stream
for the phase noise spectral characterization. The characteristics introduced between the downconverter 66 70 for the phase noise spectral characterization. The characteristics introduced between the
71 downconverter
and the decimation processing blocks are core characteristics of an oscillator characterization 67 72 and the decimation processing blocks are core characteristics of an oscillator characterization
system, and must reject out-of-band signals below the targeted phase noise -- typically in the 68 73 system, and must reject out-of-band signals below the targeted phase noise -- typically in the
sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will 69 74 sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will
use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency 70 75 use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency
datastream: optimizing the performance of the filter while reducing the needed resources is 71 76 datastream: optimizing the performance of the filter while reducing the needed resources is
hence tackled in a systematic approach using optimization techniques. Most significantly, we 72 77 hence tackled in a systematic approach using optimization techniques. Most significantly, we
tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with 73 78 tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with
tunable number of coefficients and tunable number of bits representing the coefficients and the 74 79 tunable number of coefficients and tunable number of bits representing the coefficients and the
data being processed. 75 80 data being processed.
76 81
\section{Finite impulse response filter} 77 82 \section{Finite impulse response filter}
78 83
We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined 79 84 We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined
by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the outputs $y_k$ 80 85 by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the
86 outputs $y_k$
$$y_n=\sum_{k=0}^N b_k x_{n-k}$$ 81 87 $$y_n=\sum_{k=0}^N b_k x_{n-k}$$
82 88
As opposed to an implementation on a general purpose processor in which word size is defined by the 83 89 As opposed to an implementation on a general purpose processor in which word size is defined by the
processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since 84 90 processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since
not only the coefficient values and number of taps must be defined, but also the number of bits defining 85 91 not only the coefficient values and number of taps must be defined, but also the number of bits
the coefficients and the sample size. 86 92 defining the coefficients and the sample size. For this reason, and because we consider pipeline
93 processing (as opposed to First-In, First-Out memory batch processing) of radiofrequency
94 signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
95 the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
96 Since latency is not an issue in a openloop phase noise characterization instrument, the large
97 numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
98 is not considered as an issue as would be in a closed loop system.
87 99
The coefficients are classically expressed as floating point values. However, this binary 88 100 The coefficients are classically expressed as floating point values. However, this binary
number representation is not efficient for fast arithmetic computation by an FPGA. Instead, 89 101 number representation is not efficient for fast arithmetic computation by an FPGA. Instead,
we select to quantify these floating point values into integer values. This quantization 90 102 we select to quantify these floating point values into integer values. This quantization
will result in some precision loss. As illustrated in Fig. \ref{float_vs_int}, we see that we aren't 91 103 will result in some precision loss.
need too coefficients or too sample size. If we have lot of coefficients but a small sample size, 92
the first and last are equal to zero. But if we have too sample size for few coefficients that not improve the quality. 93
94 104
105 %As illustrated in Fig. \ref{float_vs_int}, we see that we aren't
106 %need too coefficients or too sample size. If we have lot of coefficients but a small sample size,
107 %the first and last are equal to zero. But if we have too sample size for few coefficients that not improve the quality.
108
% JMF je ne comprends pas la derniere phrase ci-dessus ni la figure ci dessous 95 109 % JMF je ne comprends pas la derniere phrase ci-dessus ni la figure ci dessous
\begin{figure}[h!tb] 96 110 %\begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/float-vs-integer.pdf} 97 111 %\includegraphics[width=\linewidth]{images/float-vs-integer.pdf}
\caption{Impact of the quantization resolution of the coefficients} 98 112 %\caption{Impact of the quantization resolution of the coefficients}
%\label{float_vs_int} 99 113 %\label{float_vs_int}
\end{figure} 100 114 %\end{figure}
101 115
116 The tradeoff between quantization resolution and number of coefficients when considering
117 integer operations is not trivial. As an illustration of the issue related to the
118 relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits
119 a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon
120 quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the
121 taps become null, making the large number of coefficients irrelevant and allowing to save
122 processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources
123 to reach a given rejection level, or maximizing out of band rejection for a given computational
124 resource, will drive the investigation on cascading filters designed with varying tap resolution
125 and tap length, as will be shown in the next section.
126
\begin{figure}[h!tb] 102 127 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/demo_filtre} 103 128 \includegraphics[width=\linewidth]{images/demo_filtre}
\caption{Impact of the quantization resolution of the coefficients: the quantization is 104 129 \caption{Impact of the quantization resolution of the coefficients: the quantization is
set to 6~bits, setting the 30~first and 30~last coefficients out of the initial 128~band-pass 105 130 set to 6~bits, setting the 30~first and 30~last coefficients out of the initial 128~band-pass
filter coefficients to 0.} 106 131 filter coefficients to 0.}
\label{float_vs_int} 107 132 \label{float_vs_int}
\end{figure} 108 133 \end{figure}
109 134
110
\section{Filter optimization} 111 135 \section{Filter optimization}
112 136
A basic approach for implementing the FIR filter is to compute the transfer function of 113 137 A basic approach for implementing the FIR filter is to compute the transfer function of
a monolithic filter: this single filter defines all coefficients with the same resolution 114 138 a monolithic filter: this single filter defines all coefficients with the same resolution
(number of bits) and processes data represented with their own resolution. Meeting the 115 139 (number of bits) and processes data represented with their own resolution. Meeting the
filter shape requires a large number of coefficients, limited by resources of the FPGA since 116 140 filter shape requires a large number of coefficients, limited by resources of the FPGA since
this filter must process data stream at the radiofrequency sampling rate after the mixer. 117 141 this filter must process data stream at the radiofrequency sampling rate after the mixer.
118 142
An optimization problem \cite{leung2004handbook} aims at improving one or many 119 143 An optimization problem \cite{leung2004handbook} aims at improving one or many
performance criteria within a constrained resource environment. Amongst the tools 120 144 performance criteria within a constrained resource environment. Amongst the tools
developed to meet this aim, Mixed-Integer Linear Programming (MILP) provides the framework to 121 145 developed to meet this aim, Mixed-Integer Linear Programming (MILP) provides the framework to
provide a formal definition of the stated problem and search for an optimal use of available 122 146 provide a formal definition of the stated problem and search for an optimal use of available
resources \cite{yu2007design, kodek1980design}. 123 147 resources \cite{yu2007design, kodek1980design}.
124 148
The degrees of freedom when addressing the problem of replacing the single monolithic 125 149 The degrees of freedom when addressing the problem of replacing the single monolithic
FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$, 126 150 FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$,
the number of bits $c_i$ representing the coefficients and the number of bits $d_i$ representing 127 151 the number of bits $c_i$ representing the coefficients and the number of bits $d_i$ representing
the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage, 128 152 the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage,
the optimization of the complete processing chain within a constrained resource environment is not 129 153 the optimization of the complete processing chain within a constrained resource environment is not
trivial. The resource occupation of a FIR filter is considered as $c_i+d_i+\log_2(N_i)$ which is 130 154 trivial. The resource occupation of a FIR filter is considered as $c_i+d_i+\log_2(N_i)$ which is
the number of bits needed in a worst case condition to represent the output of the FIR. 131 155 the number of bits needed in a worst case condition to represent the output of the FIR.
132 156
133
\begin{figure}[h!tb] 134 157 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/noise-rejection.pdf} 135 158 \includegraphics[width=\linewidth]{images/noise-rejection.pdf}
\caption{Rejection as a function of number of coefficients and number of bits} 136 159 \caption{Rejection as a function of number of coefficients and number of bits}
\label{noise-rejection} 137 160 \label{noise-rejection}
\end{figure} 138 161 \end{figure}
139 162
The objective function maximizes the noise rejection while keeping resource occupation below 140 163 The objective function maximizes the noise rejection while keeping resource occupation below
a user-defined threshold. The MILP solver is allowed to choose the number of successive 141 164 a user-defined threshold. The MILP solver is allowed to choose the number of successive
filters, within an upper bound. The last problem is to model the noise rejection. Since filter 142 165 filters, within an upper bound. The last problem is to model the noise rejection. Since filter
noise rejection capability is not modeled with linear equation, a look-up-table is generated 143 166 noise rejection capability is not modeled with linear equation, a look-up-table is generated
for multiple filter configurations in which the $c_i$, $d_i$ and $N_i$ parameters are varied: for each 144 167 for multiple filter configurations in which the $c_i$, $d_i$ and $N_i$ parameters are varied: for each
one of these conditions, the low-pass filter rejection defined as the mean power between 145 168 one of these conditions, the low-pass filter rejection defined as the mean power between
half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response 146 169 half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response
of the digital filter (Fig. \ref{noise-rejection}). 147 170 of the digital filter (Fig. \ref{noise-rejection}).
148 171
Linear program formalism for solving the problem is well documented: an objective function is 149 172 Linear program formalism for solving the problem is well documented: an objective function is
defined which is linearly dependent on the parameters to be optimized. Constraints are expressed 150 173 defined which is linearly dependent on the parameters to be optimized. Constraints are expressed
as linear equation and solved using one of the available solvers, in our case GLPK\cite{glpk}. 151 174 as linear equation and solved using one of the available solvers, in our case GLPK\cite{glpk}.
152 175
The MILP solver provides a solution to the problem by selecting a series of small FIR with 153 176 The MILP solver provides a solution to the problem by selecting a series of small FIR with
increasing number of bits representing data and coefficients as well as an increasing number 154 177 increasing number of bits representing data and coefficients as well as an increasing number
of coefficients, instead of a single monolithic filter. Fig. \ref{compare-fir} exhibits the 155 178 of coefficients, instead of a single monolithic filter. Fig. \ref{compare-fir} exhibits the
performance comparison between one solution and a monolithic FIR when selecting a cutoff 156 179 performance comparison between one solution and a monolithic FIR when selecting a cutoff
frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the 157 180 frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the
same space usage are provided as selected by the MILP solver. The FIR cascade provides improved 158 181 same space usage are provided as selected by the MILP solver. The FIR cascade provides improved
rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to 159 182 rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to
be tuned or compensated for. 160 183 be tuned or compensated for.
161 184
\begin{figure}[h!tb] 162 185 \begin{figure}[h!tb]
% \includegraphics[width=\linewidth]{images/compare-fir.pdf} 163 186 % \includegraphics[width=\linewidth]{images/compare-fir.pdf}
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-200dB.pdf} 164 187 \includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-200dB.pdf}
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 165 188 \caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR
with a cutoff frequency set at half the Nyquist frequency.} 166 189 with a cutoff frequency set at half the Nyquist frequency.}
\label{compare-fir} 167 190 \label{compare-fir}
\end{figure} 168 191 \end{figure}
169 192
The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}. 170 193 The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
171 194
\begin{table}[h!tb] 172 195 \begin{table}[h!tb]
\caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade 173 196 \caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade
identified as optimal by the MILP solver within a finite resource criterion. The last line refers 174 197 identified as optimal by the MILP solver within a finite resource criterion. The last line refers
to available resources on a Zynq-7010 as found on the Redpitaya board. The rejection is the mean 175 198 to available resources on a Zynq-7010 as found on the Redpitaya board. The rejection is the mean
value from 0.6 to 1 Nyquist frequency.} 176 199 value from 0.6 to 1 Nyquist frequency.}
\begin{center} 177 200 \begin{center}
\begin{tabular}{|c|cccc|}\hline 178 201 \begin{tabular}{|c|cccc|}\hline
FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline 179 202 FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline
1 (monolithic) & 1 & 4064 & 40 & -72 \\ 180 203 1 (monolithic) & 1 & 4064 & 40 & -72 \\
5 & 5 & 12332 & 0 & -217 \\ 181 204 5 & 5 & 12332 & 0 & -217 \\
10 & 10 & 12717 & 0 & -251 \\\hline\hline 182 205 10 & 10 & 12717 & 0 & -251 \\\hline\hline
Zynq 7010 & 60 & 17600 & 80 & \\\hline 183 206 Zynq 7010 & 60 & 17600 & 80 & \\\hline
\end{tabular} 184 207 \end{tabular}
\end{center} 185 208 \end{center}
%\vspace{-0.7cm} 186 209 %\vspace{-0.7cm}
\label{t1} 187 210 \label{t1}
\end{table} 188 211 \end{table}
189 212
\section{Filter coefficient selection} 190 213 \section{Filter coefficient selection}
191 214
The coefficients of a single monolithic filter are computed as the impulse response 192 215 The coefficients of a single monolithic filter are computed as the impulse response
of the filter transfer function, and practically approximated by a multitude of methods 193 216 of the filter transfer function, and practically approximated by a multitude of methods
including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing 194 217 including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing
(Matlab's {\tt fir1} function). Cascading filters opens a new optimization opportunity by 195 218 (Matlab's {\tt fir1} function). Cascading filters opens a new optimization opportunity by
selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2} 196 219 selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2}
illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better 197 220 illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better
rejection than {\tt firls}: since the linear solver increases the number of coefficients along 198 221 rejection than {\tt firls}: since the linear solver increases the number of coefficients along
the processing chain, the type of selected filter also changes depending on the number of coefficients 199 222 the processing chain, the type of selected filter also changes depending on the number of coefficients
and evolves along the processing chain. 200 223 and evolves along the processing chain.
201 224
\begin{figure}[h!tb] 202 225 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/fir1-vs-firls} 203 226 \includegraphics[width=\linewidth]{images/fir1-vs-firls}
\caption{Evolution of the rejection capability of least-square optimized filters and Hamming 204 227 \caption{Evolution of the rejection capability of least-square optimized filters and Hamming
FIR filters as a function of the number of coefficients, for floating point numbers and 8-bit 205 228 FIR filters as a function of the number of coefficients, for floating point numbers and 8-bit
encoded integers.} 206 229 encoded integers.}
\label{2} 207 230 \label{2}
\end{figure} 208 231 \end{figure}
209 232
\section{Conclusion} 210 233 \section{Conclusion}
211 234
We address the optimization problem of designing a low-pass filter chain in a Field Programmable Gate 212 235 We address the optimization problem of designing a low-pass filter chain in a Field Programmable Gate
Array for improved noise rejection within constrained resource occupation, as needed for 213 236 Array for improved noise rejection within constrained resource occupation, as needed for
real time processing of radiofrequency signal when characterizing spectral phase noise 214 237 real time processing of radiofrequency signal when characterizing spectral phase noise
characteristics of stable oscillators. The flexibility of the digital approach makes the result 215 238 characteristics of stable oscillators. The flexibility of the digital approach makes the result
best suited for closing the loop and using the measurement output in a feedback loop for 216 239 best suited for closing the loop and using the measurement output in a feedback loop for
controlling clocks, e.g. in a quartz-stabilized high performance clock whose long term behavior 217 240 controlling clocks, e.g. in a quartz-stabilized high performance clock whose long term behavior
is controlled by non-piezoelectric resonator (sapphire resonator, microwave or optical 218 241 is controlled by non-piezoelectric resonator (sapphire resonator, microwave or optical
atomic transition). 219 242 atomic transition).
220 243
\section*{Acknowledgement} 221 244 \section*{Acknowledgement}
222 245
This work is supported by the ANR Programme d'Investissement d'Avenir in 223 246 This work is supported by the ANR Programme d'Investissement d'Avenir in
progress at the Time and Frequency Departments of the FEMTO-ST Institute 224 247 progress at the Time and Frequency Departments of the FEMTO-ST Institute
(Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e. 225 248 (Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e.
The authors would like to thank E. Rubiola, F. Vernotte, G. Cabodevila for support and 226 249 The authors would like to thank E. Rubiola, F. Vernotte, G. Cabodevila for support and
fruitful discussions. 227 250 fruitful discussions.
228 251
252
253 XXX
254
255 \subsubsection{Contraintes}
256
257 Dans les r\'ef\'erences \cite{zhuo2007scalable, olariu1993computing, pan1999improved}, les auteurs
258 proposent tous des optimisations hardware uniquement. Cependant ces articles sont focalis\'es sur des optimisations mat\'erielles
259 or notre objectif est de trouver une formalisation math\'ematique d'un FPGA.
260
261 Une dernière approche que nous avons \'etudi\'ee est l'utilisation de \emph{skeletons}. D. Crookes et A. Benkrid
262 ont beaucoup parl\'e de cette m\'ethode dans leur articles \cite{crookes1998environment, crookes2000design, benkrid2002towards}.
263 L'id\'ee essentielle est qu'ils r\'ealisent des composants très optimis\'es et param\'etrables. Ainsi lorsqu'ils
264 veulent faire un d\'eveloppement, ils utilisent les blocs d\'ejà faits.
265
266 Ces blocs repr\'esentent une \'etape de calcul (une d\'ecimation, un filtrage, une modulation, une
267 d\'emodulation etc...). En prenant le cas du FIR, on rend param\'etrables les valeurs des coefficients
268 utilis\'es pour le produit de convolutions ainsi que leur nombre. Le facteur de d\'ecimation est
269 lui aussi param\'etrable.
270
271 On gagne ainsi beaucoup de temps de d\'eveloppement car on r\'eutilise des composants d\'ejà \'eprouv\'es et optimis\'es.
272 De plus, au fil des projets, on constitue une bibliothèque de composants nous
273 permettant de faire une chaine complète très simplement.
274
275 K. Benkrid, S. Belkacemi et A. Benkrid dans leur article\cite{hide} caract\'erisent
276 ces blocs en Prolog pour faire un langage descriptif permettant d'assembler les blocs de manière
277 optimale. En partant de cette description, ils arrivent à g\'en\'erer directement le code VHDL.
278
279 \begin{itemize}
280 \item la latence du bloc repr\'esente, en coups d'horloge, le temps entre l'entr\'ee de la donn\'ee
281 et le temps où la même donn\'ee ressort du bloc.
282 \item l'acceptance repr\'esente le nombre de donn\'ees par coup d'horloge que le bloc est capable
283 de traiter.
284 \item la sortance repr\'esente le nombre de donn\'ees qui sortent par coup d'horloge.
285 \end{itemize}
286
287 Gr\^ace à cela, le logiciel est capable de donner une impl\'ementation optimale d'un problème qu'on lui
288 soumet. Le problème ne se d\'efinit pas uniquement par un r\'esultat attendu mais aussi par des
289 contraintes de d\'ebit et/ou de pr\'ecision.
290
291 Dans une second temps, nous nous sommes aussi int\'eress\'es à des articles d'ordonnancement.
292 Nous avons notamment lu des documents parlant des cas des micro-usines.
293
294 Les micro-usines ressemblent un peu à des FPGA dans le sens où on connait à l'avance les
295 t\^aches à effectuer et leurs caract\'eristiques. Nous allons donc nous inspirer
296 de leur modèle pour essayer de construire le notre.
297
298 Dans sa thèse A. Dobrila \cite{these-alex} traite d'un problème de tol\'erance aux pannes
299 dans le contextes des mirco-usines. Mais les FPGA ne sont pas concern\'es dans la mesure
300 où si le composant tombe en panne, tout le traitement est paralys\'e. Cette thèse nous a n\'eanmoins
301 permis d'avoir un exemple de formalisation de problème.
302
303 Pour finir nous avons lu la thèse de M. Coqblin \cite{these-mathias} qui elle aussi traite du sujet
304 des micro-usines. Le travail de M. Coqblin porte surtout sur une chaine de traitement
305 reconfigurable, il tient compte dans ses travaux du surcoût engendr\'e par la reconfiguration d'une machine.
306 Cela n'est pas tout à fait exploitable dans notre contexte puisqu'une
307 puce FPGA d\'es qu'elle est programm\'ee n'a pas la possibilit\'e de reconfigurer une partie de sa chaine de
308 traitement. Là encore, nous avions un exemple de formalisation d'un problème.
309
310 Pour conclure, nous avons vu deux approches li\'ees à deux domaines diff\'erents. La première est le
311 point de vue \'electronique qui se focalise principalement sur des optimisations mat\'erielles ou algorithmiques.
312 La seconde est le point de vue informatique : les modèles sont très g\'en\'eriques et ne sont pas
313 adapt\'es au cas des FPGA. La suite de ce rapport se concentrera donc sur la recherche d'un compromis
314 entre ces deux points de vue.
315
316 \section{Contexte d'ordonnancement}
317 Dans cette partie, nous donnerons des d\'efinitions de termes rattach\'es au domaine de l'ordonnancement
318 et nous verrons que le sujet trait\'e se rapproche beaucoup d'un problème d'ordonnancement. De ce fait
319 nous pourrons aller plus loin que les travaux vus pr\'ec\'edemment et nous tenterons des approches d'ordonnancement
320 et d'optimisation.
321
322 \subsection{D\'efinition du vocabulaire}
323 Avant tout, il faut d\'efinir ce qu'est un problème d'optimisation. Il y a deux d\'efinitions
324 importantes à donner. La première est propos\'ee par Legrand et Robert dans leur livre \cite{def1-ordo} :
325 \begin{definition}
326 \label{def-ordo1}
327 Un ordonnancement d'un système de t\^aches $G\ =\ (V,\ E,\ w)$ est une fonction $\sigma$ :
328 $V \rightarrow \mathbb{N}$ telle que $\sigma(u) + w(u) \leq \sigma(v)$ pour toute arête $(u,\ v) \in E$.
329 \end{definition}
330
331 Dit plus simplement, l'ensemble $V$ repr\'esente les t\^aches à ex\'ecuter, l'ensemble $E$ repr\'esente les d\'ependances
332 des t\^aches et $w$ les temps d'ex\'ecution de la t\^ache. La fonction $\sigma$ donne donc l'heure de d\'ebut de
333 chacune des t\^aches. La d\'efinition dit que si une t\^ache $v$ d\'epend d'une t\^ache $u$ alors
334 la date de d\'ebut de $v$ sera plus grande ou \'egale au d\'ebut de l'ex\'ecution de la t\^ache $u$ plus son
335 temps d'ex\'ecution.
336
337 Une autre d\'efinition importante qui est propos\'ee par Leung et al. \cite{def2-ordo} est :
338 \begin{definition}
339 \label{def-ordo2}
340 L'ordonnancement traite de l'allocation de ressources rares à des activit\'es avec
341 l'objectif d'optimiser un ou plusieurs critères de performance.
342 \end{definition}
343
344 Cette d\'efinition est plus g\'en\'erique mais elle nous int\'eresse d'avantage que la d\'efinition \ref{def-ordo1}.
345 En effet, la partie qui nous int\'eresse dans cette première d\'efinition est le respect de la pr\'ec\'edance des t\^aches.
346 Dans les faits les dates de d\'ebut ne nous int\'eressent pas r\'eellement.
347
348 En revanche la d\'efinition \ref{def-ordo2} sera au c\oe{}ur du projet. Pour se convaincre de cela,
349 il nous faut d'abord d\'efinir quel est le type de problème d'ordonnancement qu'on traite et quelles
350 sont les m\'ethodes qu'on peut appliquer.
351
352 Les problèmes d'ordonnancement peuvent être class\'es en diff\'erentes cat\'egories :
353 \begin{itemize}
354 \item T\^aches ind\'ependantes : dans cette cat\'egorie de problèmes, les t\^aches sont complètement ind\'ependantes
355 les unes des autres. Dans notre cas, ce n'est pas le plus adapt\'e.
356 \item Graphe de t\^aches : la d\'efinition \ref{def-ordo1} d\'ecrit cette cat\'egorie. La plupart du temps,
357 les t\^aches sont repr\'esent\'ees par une DAG. Cette cat\'egorie est très proche de notre cas puisque nous devons \'egalement ex\'ecuter
358 des t\^aches qui ont un certain nombre de d\'ependances. On pourra même dire que dans certain cas,
359 on a des anti-arbres, c'est à dire que nous avons une multitude de t\^aches d'entr\'ees qui convergent vers une
360 t\^ache de fin.
361 \item Workflow : cette cat\'egorie est une sous cat\'egorie des graphes de t\^aches dans le sens où
362 il s'agit d'un graphe de t\^aches r\'ep\'et\'e de nombreuses de fois. C'est exactement ce type de problème
363 que nous traitons ici.
364 \end{itemize}
365
366 Bien entendu, cette liste n'est pas exhaustive et il existe de nombreuses autres classifications et sous-classifications
367 de ces problèmes. Nous n'avons parl\'e ici que des cat\'egories les plus communes.
368
369 Un autre point à d\'efinir, est le critère d'optimisation. Il y a là encore un grand nombre de
370 critères possibles. Nous allons donc parler des principaux :
371 \begin{itemize}
372 \item Temps de compl\'etion total (ou Makespan en anglais) : ce critère est l'un des critères d'optimisation
373 les plus courant. Il s'agit donc de minimiser la date de fin de la dernière t\^ache de l'ensemble des
374 t\^aches à ex\'ecuter. L'enjeu de cette optimisation est donc de trouver l'ordonnancement optimal permettant
375 la fin d'ex\'ecution au plus tôt.
376 \item Somme des temps d'ex\'ecution (Flowtime en anglais) : il s'agit de faire la somme des temps d'ex\'ecution de toutes les t\^aches
377 et d'optimiser ce r\'esultat.
378 \item Le d\'ebit : ce critère quant à lui, vise à augmenter au maximum le d\'ebit de traitement des donn\'ees.
379 \end{itemize}
380
381 En plus de cela, on peut avoir besoin de plusieurs critères d'optimisation. Il s'agit dans ce cas d'une optimisation
382 multi-critères. Bien entendu, cela complexifie d'autant plus le problème car la solution la plus optimale pour un
383 des critères peut être très mauvaise pour un autre critère. De ce cas, il s'agira de trouver une solution qui permet
384 de faire le meilleur compromis entre tous les critères.
385
386
387 \subsection{Formalisation du problème}
388 \label{formalisation}
389 Maintenant que nous avons donn\'e le vocabulaire li\'e à l'ordonnancement, nous allons pouvoir essayer caract\'eriser
390 formellement notre problème. En effet, nous allons reprendre les contraintes \'enonc\'ees dans la sections \ref{def-contraintes}
391 et nous essayerons de les formaliser le plus finement possible.
392
393 Comme nous l'avons dit, une t\^ache est un bloc de traitement. Chaque t\^ache $i$ dispose d'un ensemble de paramètres
394 que nous nommerons $\mathcal{P}_{i}$. Cet ensemble $\mathcal{P}_i$ est propre à chaque t\^ache et il variera d'une
395 t\^ache à l'autre. Nous reviendrons plus tard sur les paramètres qui peuvent composer cet ensemble.
396
397 Outre cet ensemble $\mathcal{P}_i$, chaque t\^ache dispose de paramètres communs :
398 \begin{itemize}
399 \item Dur\'ee de la t\^ache : Comme nous l'avons dit auparavant, dans le cadre d'un FPGA le temps est compt\'e en nombre de coup d'horloge.
400 En outre, les blocs sont toujours sollicit\'es, certains même sont capables de lire et de renvoyer une r\'esultat à chaque coups d'horloge.
401 Donc la dur\'ee d'une t\^ache ne peut être le laps de temps entre l'entr\'ee d'une donn\'ee et la sortie d'une autre. Nous d\'efinirons la
402 dur\'ee comme le temps de traitement d'une donn\'ee, c'est à dire la diff\'erence de temps entre la date de sortie d'une donn\'ee
403 et de sa date d'entr\'ee. Nous nommerons cette dur\'ee $\delta_i$. % Je devrais la nomm\'ee w comme dans la def2
404 \item La pr\'ecision : La pr\'ecision d'une donn\'ee est le nombre de bits significatifs qu'elle compte. En effet, au fil des traitements
405 les pr\'ecisions peuvent varier. On nomme donc la pr\'ecision d'entr\'ee d'une t\^ache $i$ comme $\pi_i^-$ et la pr\'ecision en sortie $\pi_i^+$.
406 \item La fr\'equence du flux en entr\'ee (ou sortie) : Cette fr\'equence repr\'esente la fr\'equence des donn\'ees qui arrivent (resp. sortent).
407 Selon les t\^aches, les fr\'equences varieront. En effet, certains blocs ralentissent le flux c'est pourquoi on distingue la fr\'equence du
408 flux en entr\'ee et la fr\'equence en sortie. Nous nommerons donc la fr\'equence du flux en entr\'ee $f_i^-$ et la fr\'equence en sortie $f_i^+$.
409 \item La quantit\'e de donn\'ees en entr\'ee (ou en sortie) : Il s'agit de la quantit\'e de donn\'ees que le bloc s'attend à traiter (resp.
410 est capable de produire). Les t\^aches peuvent avoir à traiter des gros volumes de donn\'ees et n'en ressortir qu'une partie. Cette
411 fois encore, il nous faut donc diff\'erencier l'entr\'ee et la sortie. Nous nommerons donc la quantit\'e de donn\'ees entrantes $q_i^-$
412 et la quantit\'e de donn\'ees sortantes $q_i^+$ pour une t\^ache $i$.
413 \item Le d\'ebit d'entr\'ee (ou de sortie) : Ce paramètre correspond au d\'ebit de donn\'ees que la t\^ache est capable de traiter ou qu'elle
414 fournit en sortie. Il s'agit simplement de l'expression des deux pr\'ec\'edents paramètres. Nous d\'efinirons donc la d\'ebit entrant de la
415 t\^ache $i$ comme $d_i^-\ =\ q_i^-\ *\ f_i^-$ et le d\'ebit sortant comme $d_i^+\ =\ q_i^+\ *\ f_i^+$.
416 \item La taille de la t\^ache : La taille dans les FPGA \'etant limit\'ee, ce paramètre exprime donc la place qu'occupe la t\^ache au sein du bloc.
417 Nous nommerons $\mathcal{A}_i$ cette taille.
418 \item Les pr\'ed\'ecesseurs et successeurs d'une t\^ache : cela nous permet de connaître les t\^aches requises pour pouvoir traiter
419 la t\^ache $i$ ainsi que les t\^aches qui en d\'ependent. Ces ensemble sont not\'es $\Gamma _i ^-$ et $ \Gamma _i ^+$ \\
420 %TODO Est-ce vraiment un paramètre ?
421 \end{itemize}
422
423 Ces diff\'erents paramètres communs sont fortement li\'es aux \'el\'ements de $\mathcal{P}_i$. Voici quelques exemples de relations
424 que nous avons identifi\'ees :
425 \begin{itemize}
426 \item $ \delta _i ^+ \ = \ \mathcal{F}_{\delta}(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+,\ \mathcal{P}_i) $ donne le temps d'ex\'ecution
427 de la t\^ache en fonction de la pr\'ecision voulue, du d\'ebit et des paramètres internes.
428 \item $ \pi _i ^+ \ = \ \mathcal{F}_{p}(\pi_i^-,\ \mathcal{P}_i) $, la fonction $F_p$ donne la pr\'ecision en sortie selon la pr\'ecision de d\'epart
429 et les paramètres internes de la t\^ache.
430 \item $d_i^+\ =\ \mathcal{F}_d(d_i^-, \mathcal{P}_i)$, la fonction $F_d$ donne le d\'ebit sortant de la t\^ache en fonction du d\'ebit
431 sortant et des variables internes de la t\^ache.
432 \item $A_i^+\ =\ \mathcal{F}_A(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+, \mathcal{P}_i)$
433 \end{itemize}
434 Pour le moment, nous ne sommes pas capables de donner une d\'efinition g\'en\'erale de ces fonctions. Mais en revanche,
435 sur quelques exemples simples (cf. \ref{def-contraintes}), nous parvenons à donner une \'evaluation de ces fonctions.
436
437 Maintenant que nous avons donn\'e toutes les notations utiles, nous allons \'enoncer des contraintes relatives à notre problème. Soit
438 un DGA $G(V,\ E)$, on a pour toutes arêtes $(i, j)\ \in\ E$ les in\'equations suivantes :
439
440 \paragraph{Contrainte de pr\'ecision :}
441 Cette in\'equation traduit la contrainte de pr\'ecision d'une t\^ache à l'autre :
442 \begin{align*}
443 \pi _i ^+ \geq \pi _j ^-
444 \end{align*}
445
446 \paragraph{Contrainte de d\'ebit :}
447 Cette in\'equation traduit la contrainte de d\'ebit d'une t\^ache à l'autre :
448 \begin{align*}
449 d _i ^+ = q _j ^- * (f_i + (1 / s_j) ) & \text{ où } s_j \text{ est une valeur positive de temporisation de la t\^ache}
450 \end{align*}
451
452 \paragraph{Contrainte de synchronisation :}
453 Il s'agit de la contrainte qui impose que si à un moment du traitement, le DAG se s\'epare en plusieurs branches parallèles
454 et qu'elles se rejoignent plus tard, la somme des latences sur chacune des branches soit la même.
455 Plus formellement, s'il existe plusieurs chemins disjoints, partant de la t\^ache $s$ et allant à la t\^ache de $f$ alors :
456 \begin{align*}
457 \forall \text{ chemin } \mathcal{C}1(s, .., f),
458 \forall \text{ chemin } \mathcal{C}2(s, .., f)
459 \text{ tel que } \mathcal{C}1 \neq \mathcal{C}2
460 \Rightarrow
461 \sum _{i} ^{i \in \mathcal{C}1} \delta_i = \sum _{i} ^{i \in \mathcal{C}2} \delta_i
462 \end{align*}
463
464 \paragraph{Contrainte de place :}
465 Cette in\'equation traduit la contrainte de place dans le FPGA. La taille max de la puce FPGA est nomm\'e $\mathcal{A}_{FPGA}$ :
466 \begin{align*}
467 \sum ^{\text{t\^ache } i} \mathcal{A}_i \leq \mathcal{A}_{FPGA}
468 \end{align*}
469
470 \subsection{Exemples de mod\'elisation}
471 \label{exemples-modeles}
472 Nous allons maintenant prendre quelques blocs de traitement simples afin d'illustrer au mieux notre modèle.
473 Pour tous nos exemple, nous prendrons un d\'ebit en entr\'ee de 200 Mo/s avec une pr\'ecision de 16 bit.
474
475 Prenons tout d'abord l'exemple d'un bloc de d\'ecimation. Le but de ce bloc est de ralentir le flux en ne gardant
476 que certaines donn\'ees à intervalle r\'egulier. Cet intervalle est appel\'e le facteur de d\'ecimation, on le notera $N$.
477
478 Donc d'après notre mod\'elisation :
479 \begin{itemize}
480 \item $N \in \mathcal{P}_i$
481 %TODO N ou 1 ?
482 \item $\delta _i = N\ c.h.$ (coup d'horloge)
483 \item $\pi _i ^+ = \pi _i ^- = 16 bits$
484 \item $f _i ^+ = f _i ^-$
485 \item $q _i ^+ = q _i ^- / N$
486 \item $d _i ^+ = q _i ^- / N / f _i ^-$
487 \item $\Gamma _i ^+ = \Gamma _i ^- = 1$\\
488 %TODO Je ne sais pas trouver la taille...
489 \end{itemize}
490
491 Un autre exemple int\'eressant que l'on peut donner, c'est le cas des spliters. Il s'agit la aussi d'un bloc très
492 simple qui permet de dupliquer un flux. On peut donc donner un nombre de sorties à cr\'eer, on note ce paramètre
493 %TODO pas très inspir\'e...
494 $X$. Voici ce que donne notre mod\'elisation :
495 \begin{itemize}
496 \item $X \in \mathcal{P}_i$
497 \item $\delta _i = 1\ c.h.$
498 \item $\pi _i ^+ = \pi _i ^- = 16 bits$
499 \item $f _i ^+ = f _i ^-$
500 \item $q _i ^+ = q _i ^-$
501 \item $d _i ^+ = d _i ^-$
502 \item $\Gamma _i ^- = 1$
503 \item $\Gamma _i ^+ = X$\\
504 \end{itemize}
505
506 L'exemple suivant traite du cas du shifter. Il s'agit d'un bloc qui a pour but de diminuer le nombre de bits des
507 donn\'ees afin d'acc\'el\'erer les traitement sur les blocs suivants. On peut donc donner le nombre de bits à shifter,
508 on note ce paramètre $S$. Voici ce que donne notre mod\'elisation :
509 \begin{itemize}
510 \item $S \in \mathcal{P}_i$
511 \item $\delta _i = 1\ c.h.$
512 \item $\pi _i ^+ = \pi _i ^- - S$
513 \item $f _i ^+ = f _i ^-$
514 \item $q _i ^+ = q _i ^-$
515 \item $d _i ^+ = d _i ^-$
516 \item $\Gamma _i ^+ = \Gamma _i ^- = 1$\\
517 \end{itemize}
518
519 Nous allons traiter un dernier exemple un peu plus complexe, le cas d'un filtre d\'ecimateur (ou FIR). Ce bloc
520 est compos\'e de beaucoup de paramètres internes. On peut d\'efinir un nombre d'\'etages $E$, qui repr\'esente le nombre
521 d'it\'erations à faire avant d'arrêter le traitement. Afin d'effectuer son filtrage, on doit donner au bloc un ensemble
522 de coefficients $C$ et par cons\'equent ces coefficients ont leur propre pr\'ecision $\pi _C$. Pour finir, le dernier
523 paramètre à donner est le facteur de d\'ecimation $N$. Si on applique notre mod\'elisation, on peut obtenir cela :