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ifcs2018_proceeding.tex
\documentclass[a4paper,conference]{IEEEtran/IEEEtran} 1 1 \documentclass[a4paper,conference]{IEEEtran/IEEEtran}
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\begin{document} 15 15 \begin{document}
\title{Filter optimization for real time digital processing of radiofrequency signals: application 16 16 \title{Filter optimization for real time digital processing of radiofrequency signals: application
to oscillator metrology} 17 17 to oscillator metrology}
18 18
\author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2}, 19 19 \author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2},
G. Goavec-M\'erou\IEEEauthorrefmark{1}, 20 20 G. Goavec-M\'erou\IEEEauthorrefmark{1},
P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}} 21 21 P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}}
\IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France } 22 22 \IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France }
\IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\ 23 23 \IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\
Email: \{pyb2,jmfriedt\}@femto-st.fr} 24 24 Email: \{pyb2,jmfriedt\}@femto-st.fr}
} 25 25 }
\maketitle 26 26 \maketitle
\thispagestyle{plain} 27 27 \thispagestyle{plain}
\pagestyle{plain} 28 28 \pagestyle{plain}
\newtheorem{definition}{Definition} 29 29 \newtheorem{definition}{Definition}
30 30
\begin{abstract} 31 31 \begin{abstract}
Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to 32 32 Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to
radiofrequency signal processing. Applied to oscillator characterization in the context 33 33 radiofrequency signal processing. Applied to oscillator characterization in the context
of ultrastable clocks, stringent filtering requirements are defined by spurious signal or 34 34 of ultrastable clocks, stringent filtering requirements are defined by spurious signal or
noise rejection needs. Since real time radiofrequency processing must be performed in a 35 35 noise rejection needs. Since real time radiofrequency processing must be performed in a
Field Programmable Array to meet timing constraints, we investigate optimization strategies 36 36 Field Programmable Array to meet timing constraints, we investigate optimization strategies
to design filters meeting rejection characteristics while limiting the hardware resources 37 37 to design filters meeting rejection characteristics while limiting the hardware resources
required and keeping timing constraints within the targeted measurement bandwidths. 38 38 required and keeping timing constraints within the targeted measurement bandwidths.
\end{abstract} 39 39 \end{abstract}
40 40
\begin{IEEEkeywords} 41 41 \begin{IEEEkeywords}
Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter 42 42 Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter
\end{IEEEkeywords} 43 43 \end{IEEEkeywords}
44 44
\section{Digital signal processing of ultrastable clock signals} 45 45 \section{Digital signal processing of ultrastable clock signals}
46 46
Analog oscillator phase noise characteristics are classically performed by downconverting 47 47 Analog oscillator phase noise characteristics are classically performed by downconverting
the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband, 48 48 the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband,
followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In 49 49 followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In
a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by 50 50 a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by
multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}. 51 51 multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}.
52 52
\begin{figure}[h!tb] 53 53 \begin{figure}[h!tb]
\begin{center} 54 54 \begin{center}
\includegraphics[width=.8\linewidth]{images/schema} 55 55 \includegraphics[width=.8\linewidth]{images/schema}
\end{center} 56 56 \end{center}
\caption{Fully digital oscillator phase noise characterization: the Device Under Test 57 57 \caption{Fully digital oscillator phase noise characterization: the Device Under Test
(DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and 58 58 (DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and
downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals 59 59 downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals
and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite 60 60 and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite
Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays 61 61 Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays
the spectral characteristics of the phase fluctuations.} 62 62 the spectral characteristics of the phase fluctuations.}
\label{schema} 63 63 \label{schema}
\end{figure} 64 64 \end{figure}
65 65
As with the analog mixer, 66 66 As with the analog mixer,
the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as 67 67 the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as
well as the generation of the frequency sum signal in addition to the frequency difference. 68 68 well as the generation of the frequency sum signal in addition to the frequency difference.
These unwanted spectral characteristics must be rejected before decimating the data stream 69 69 These unwanted spectral characteristics must be rejected before decimating the data stream
for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the 70 70 for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the
downconverter 71 71 downconverter
and the decimation processing blocks are core characteristics of an oscillator characterization 72 72 and the decimation processing blocks are core characteristics of an oscillator characterization
system, and must reject out-of-band signals below the targeted phase noise -- typically in the 73 73 system, and must reject out-of-band signals below the targeted phase noise -- typically in the
sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will 74 74 sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will
use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency 75 75 use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency
datastream: optimizing the performance of the filter while reducing the needed resources is 76 76 datastream: optimizing the performance of the filter while reducing the needed resources is
hence tackled in a systematic approach using optimization techniques. Most significantly, we 77 77 hence tackled in a systematic approach using optimization techniques. Most significantly, we
tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with 78 78 tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with
tunable number of coefficients and tunable number of bits representing the coefficients and the 79 79 tunable number of coefficients and tunable number of bits representing the coefficients and the
data being processed. 80 80 data being processed.
81 81
\section{Finite impulse response filter} 82 82 \section{Finite impulse response filter}
83 83
We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined 84 84 We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined
by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the 85 85 by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the
outputs $y_k$ 86 86 outputs $y_k$
$$y_n=\sum_{k=0}^N b_k x_{n-k}$$ 87 87 $$y_n=\sum_{k=0}^N b_k x_{n-k}$$
88 88
As opposed to an implementation on a general purpose processor in which word size is defined by the 89 89 As opposed to an implementation on a general purpose processor in which word size is defined by the
processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since 90 90 processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since
not only the coefficient values and number of taps must be defined, but also the number of bits 91 91 not only the coefficient values and number of taps must be defined, but also the number of bits
defining the coefficients and the sample size. For this reason, and because we consider pipeline 92 92 defining the coefficients and the sample size. For this reason, and because we consider pipeline
processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency 93 93 processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency
signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but 94 94 signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but
the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL). 95 95 the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL).
Since latency is not an issue in a openloop phase noise characterization instrument, the large 96 96 Since latency is not an issue in a openloop phase noise characterization instrument, the large
numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter, 97 97 numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter,
is not considered as an issue as would be in a closed loop system. 98 98 is not considered as an issue as would be in a closed loop system.
99 99
The coefficients are classically expressed as floating point values. However, this binary 100 100 The coefficients are classically expressed as floating point values. However, this binary
number representation is not efficient for fast arithmetic computation by an FPGA. Instead, 101 101 number representation is not efficient for fast arithmetic computation by an FPGA. Instead,
we select to quantify these floating point values into integer values. This quantization 102 102 we select to quantify these floating point values into integer values. This quantization
will result in some precision loss. 103 103 will result in some precision loss.
104 104
%As illustrated in Fig. \ref{float_vs_int}, we see that we aren't 105 105 %As illustrated in Fig. \ref{float_vs_int}, we see that we aren't
%need too coefficients or too sample size. If we have lot of coefficients but a small sample size, 106 106 %need too coefficients or too sample size. If we have lot of coefficients but a small sample size,
%the first and last are equal to zero. But if we have too sample size for few coefficients that not improve the quality. 107 107 %the first and last are equal to zero. But if we have too sample size for few coefficients that not improve the quality.
108 108
% JMF je ne comprends pas la derniere phrase ci-dessus ni la figure ci dessous 109 109 % JMF je ne comprends pas la derniere phrase ci-dessus ni la figure ci dessous
% AH en gros je voulais dire que prendre trop peu de bit avec trop de coeff, ça induit ta figure (bien mieux faite que moi) 110 110 % AH en gros je voulais dire que prendre trop peu de bit avec trop de coeff, ça induit ta figure (bien mieux faite que moi)
% et que l'inverse trop de bit sur pas assez de coeff on ne gagne rien, je vais essayer de la reformuler 111 111 % et que l'inverse trop de bit sur pas assez de coeff on ne gagne rien, je vais essayer de la reformuler
112 112
%\begin{figure}[h!tb] 113 113 %\begin{figure}[h!tb]
%\includegraphics[width=\linewidth]{images/float-vs-integer.pdf} 114 114 %\includegraphics[width=\linewidth]{images/float-vs-integer.pdf}
%\caption{Impact of the quantization resolution of the coefficients} 115 115 %\caption{Impact of the quantization resolution of the coefficients}
%\label{float_vs_int} 116 116 %\label{float_vs_int}
%\end{figure} 117 117 %\end{figure}
118 118
\begin{figure}[h!tb] 119 119 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/demo_filtre} 120 120 \includegraphics[width=\linewidth]{images/demo_filtre}
\caption{Impact of the quantization resolution of the coefficients: the quantization is 121 121 \caption{Impact of the quantization resolution of the coefficients: the quantization is
set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting 122 122 set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting
the 30~first and 30~last coefficients out of the initial 128~band-pass 123 123 the 30~first and 30~last coefficients out of the initial 128~band-pass
filter coefficients to 0 (red dots).} 124 124 filter coefficients to 0 (red dots).}
\label{float_vs_int} 125 125 \label{float_vs_int}
\end{figure} 126 126 \end{figure}
127 127
The tradeoff between quantization resolution and number of coefficients when considering 128 128 The tradeoff between quantization resolution and number of coefficients when considering
integer operations is not trivial. As an illustration of the issue related to the 129 129 integer operations is not trivial. As an illustration of the issue related to the
relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits 130 130 relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits
a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon 131 131 a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon
quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the 132 132 quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the
taps become null, making the large number of coefficients irrelevant and allowing to save 133 133 taps become null, making the large number of coefficients irrelevant and allowing to save
processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources 134 134 processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources
to reach a given rejection level, or maximizing out of band rejection for a given computational 135 135 to reach a given rejection level, or maximizing out of band rejection for a given computational
resource, will drive the investigation on cascading filters designed with varying tap resolution 136 136 resource, will drive the investigation on cascading filters designed with varying tap resolution
and tap length, as will be shown in the next section. Indeed, our development strategy closely 137 137 and tap length, as will be shown in the next section. Indeed, our development strategy closely
follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards} 138 138 follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards}
in which basic blocks are defined and characterized before being assembled \cite{hide} 139 139 in which basic blocks are defined and characterized before being assembled \cite{hide}
in a complete processing chain. In our case, assembling the filter blocks is a simpler block 140 140 in a complete processing chain. In our case, assembling the filter blocks is a simpler block
combination process since we assume a single value to be processed and a single value to be 141 141 combination process since we assume a single value to be processed and a single value to be
generated at each clock cycle. The FIR filters will not be considered to decimate in the 142 142 generated at each clock cycle. The FIR filters will not be considered to decimate in the
current implementation: the decimation is assumed to be located after the FIR cascade at the 143 143 current implementation: the decimation is assumed to be located after the FIR cascade at the
moment. 144 144 moment.
145 145
\section{Filter optimization} 146 146 \section{Filter optimization}
147 147
A basic approach for implementing the FIR filter is to compute the transfer function of 148 148 A basic approach for implementing the FIR filter is to compute the transfer function of
a monolithic filter: this single filter defines all coefficients with the same resolution 149 149 a monolithic filter: this single filter defines all coefficients with the same resolution
(number of bits) and processes data represented with their own resolution. Meeting the 150 150 (number of bits) and processes data represented with their own resolution. Meeting the
filter shape requires a large number of coefficients, limited by resources of the FPGA since 151 151 filter shape requires a large number of coefficients, limited by resources of the FPGA since
this filter must process data stream at the radiofrequency sampling rate after the mixer. 152 152 this filter must process data stream at the radiofrequency sampling rate after the mixer.
153 153
An optimization problem \cite{leung2004handbook} aims at improving one or many 154 154 An optimization problem \cite{leung2004handbook} aims at improving one or many
performance criteria within a constrained resource environment. Amongst the tools 155 155 performance criteria within a constrained resource environment. Amongst the tools
developed to meet this aim, Mixed-Integer Linear Programming (MILP) provides the framework to 156 156 developed to meet this aim, Mixed-Integer Linear Programming (MILP) provides the framework to
formally define the stated problem and search for an optimal use of available 157 157 formally define the stated problem and search for an optimal use of available
resources \cite{yu2007design, kodek1980design}. 158 158 resources \cite{yu2007design, kodek1980design}.
159 159
First we need to ensure that our problem is a real optimization problem. When 160 160 First we need to ensure that our problem is a real optimization problem. When
designing a processing function in the FPGA, we aim at meeting some requirement such as 161 161 designing a processing function in the FPGA, we aim at meeting some requirement such as
the throughput, the computation time or the noise rejection noise. However, due to limited 162 162 the throughput, the computation time or the noise rejection noise. However, due to limited
resources to design the process like BRAM (high performance RAM), DSP (Digital Signal Processor) 163 163 resources to design the process like BRAM (high performance RAM), DSP (Digital Signal Processor)
or LUT (Look Up Table), a tradeoff must be generally searched between performance and available 164 164 or LUT (Look Up Table), a tradeoff must be generally searched between performance and available
computational resources: optimizing some criteria within finite, limited 165 165 computational resources: optimizing some criteria within finite, limited
resources indeed matches the definition of a classical optimization problem. 166 166 resources indeed matches the definition of a classical optimization problem.
167 167
Specifically the degrees of freedom when addressing the problem of replacing the single monolithic 168 168 Specifically the degrees of freedom when addressing the problem of replacing the single monolithic
FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$, 169 169 FIR with a cascade of optimized filters are the number of coefficients $N_i$ of each filter $i$,
the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ representing 170 170 the number of bits $C_i$ representing the coefficients and the number of bits $D_i$ representing
the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage, 171 171 the data fed to the filter. Because each FIR in the chain is fed the output of the previous stage,
the optimization of the complete processing chain within a constrained resource environment is not 172 172 the optimization of the complete processing chain within a constrained resource environment is not
trivial. The resource occupation of a FIR filter is considered as $(D_i+C_i) \times N_i$ which is 173 173 trivial. The resource occupation of a FIR filter is considered as $(D_i+C_i) \times N_i$ which is
the number of bits needed in a worst case condition to represent the output of the FIR. Such an 174 174 the number of bits needed in a worst case condition to represent the output of the FIR. Such an
occupied area estimate assumes that the number of gates scales as the number of bits and the number 175 175 occupied area estimate assumes that the number of gates scales as the number of bits and the number
of coefficients, but does not account for the detailed implementation of the hardware. Indeed, 176 176 of coefficients, but does not account for the detailed implementation of the hardware. Indeed,
various FPGA implementations will provide different hardware functionalities, and we shall consider 177 177 various FPGA implementations will provide different hardware functionalities, and we shall consider
at the end of the design a synthesis step using vendor software to assess the validity of the solution 178 178 at the end of the design a synthesis step using vendor software to assess the validity of the solution
found. As an example of the limitation linked to the lack of detailed hardware consideration, Block Random 179 179 found. As an example of the limitation linked to the lack of detailed hardware consideration, Block Random
Access Memory (BRAM) used to store filter coefficients are not shared amongst filters, and multiplications 180 180 Access Memory (BRAM) used to store filter coefficients are not shared amongst filters, and multiplications
are most efficiently implemented by using DSP blocks whose input word 181 181 are most efficiently implemented by using DSP blocks whose input word
size is finite. DSPs are a scarce resource to be saved in a practical implementation. Keeping a high 182 182 size is finite. DSPs are a scarce resource to be saved in a practical implementation. Keeping a high
abstraction on the resource occupation is nevertheless selected in the following discussion in order 183 183 abstraction on the resource occupation is nevertheless selected in the following discussion in order
to leave enough degrees of freedom in the problem to try and find original solutions: too many 184 184 to leave enough degrees of freedom in the problem to try and find original solutions: too many
constraints in the initial statement of the problem leave little room for finding an optimal solution. 185 185 constraints in the initial statement of the problem leave little room for finding an optimal solution.
186 186
\begin{figure}[h!tb] 187 187 \begin{figure}[h!tb]
\begin{center} 188 188 \begin{center}
\includegraphics[width=.5\linewidth]{schema2} 189 189 \includegraphics[width=.5\linewidth]{schema2}
\caption{Shape of the filter transmitted power $P$ as a function of frequency: 190 190 \caption{Shape of the filter transmitted power $P$ as a function of frequency:
the bandpass BP is considered to occupy the initial 191 191 the bandpass BP is considered to occupy the initial
40\% of the Nyquist frequency range, the stopband the last 40\%, allowing 20\% transition 192 192 40\% of the Nyquist frequency range, the stopband the last 40\%, allowing 20\% transition
width.} 193 193 width.}
\label{rejection-shape} 194 194 \label{rejection-shape}
\end{center} 195 195 \end{center}
\end{figure} 196 196 \end{figure}
197 197
Following these considerations, the model is expressed as: 198 198 Following these considerations, the model is expressed as:
\begin{align} 199 199 \begin{align}
\begin{cases} 200 200 \begin{cases}
\mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\ 201 201 \mathcal{R}_i &= \mathcal{F}(N_i, C_i)\\
\mathcal{A}_i &= N_i * C_i + D_i\\ 202 202 \mathcal{A}_i &= N_i * C_i + D_i\\
\Delta_i &= \Delta _{i-1} + \mathcal{P}_i 203 203 \Delta_i &= \Delta _{i-1} + \mathcal{P}_i
\end{cases} 204 204 \end{cases}
\label{model-FIR} 205 205 \label{model-FIR}
\end{align} 206 206 \end{align}
To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$ 207 207 To explain the system \ref{model-FIR}, $\mathcal{R}_i$ represents the rejection of depending on $N_i$ and $C_i$, $\mathcal{A}$
is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$. 208 208 is a theoretical area occupation of the processing block on the FPGA, and $\Delta_i$ is the total rejection for the current stage $i$.
Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending 209 209 Since the function $\mathcal{F}$ cannot be explictly expressed, we run simulations to determine the rejection depending
on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an 210 210 on $N_i$ and $C_i$. However, selecting the right filter requires a clear definition of the rejection criterion. Selecting an
incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements. 211 211 incorrect criterion will lead the linear program solver to produce a solution which might not meet the user requirements.
Hence, amongst various criteria including the mean or median value of the FIR response in the stopband as will 212 212 Hence, amongst various criteria including the mean or median value of the FIR response in the stopband as will
be illustrated lated (section \ref{median}), we have designed 213 213 be illustrated lated (section \ref{median}), we have designed
a criterion aimed at avoiding ripples in the passband and considering the maximum of the FIR spectral response in the stopband 214 214 a criterion aimed at avoiding ripples in the passband and considering the maximum of the FIR spectral response in the stopband
(Fig. \ref{rejection-shape}). The bandpass criterion is defined as the sum of the absolute values of the spectral response 215 215 (Fig. \ref{rejection-shape}). The bandpass criterion is defined as the sum of the absolute values of the spectral response
in the bandpass, reminiscent of a standard deviation of the spectral response: this criterion must be minimized to avoid 216 216 in the bandpass, reminiscent of a standard deviation of the spectral response: this criterion must be minimized to avoid
ripples in the passband. The stopband transfer function maximum must also be minimized in order to improve the filter 217 217 ripples in the passband. The stopband transfer function maximum must also be minimized in order to improve the filter
rejection capability. Weighing these two criteria allows designing the linear program to be solved. 218 218 rejection capability. Weighing these two criteria allows designing the linear program to be solved.
219 219
\begin{figure}[h!tb] 220 220 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/noise-rejection.pdf} 221 221 \includegraphics[width=\linewidth]{images/noise-rejection.pdf}
\caption{Rejection as a function of number of coefficients and number of bits} 222 222 \caption{Rejection as a function of number of coefficients and number of bits}
\label{noise-rejection} 223 223 \label{noise-rejection}
\end{figure} 224 224 \end{figure}
225 225
The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below 226 226 The objective function maximizes the noise rejection ($\max(\Delta_{i_{\max}})$) while keeping resource occupation below
a user-defined threshold. The MILP solver is allowed to choose the number of successive 227 227 a user-defined threshold. The MILP solver is allowed to choose the number of successive
filters, within an upper bound. The last problem is to model the noise rejection. Since filter 228 228 filters, within an upper bound. The last problem is to model the noise rejection. Since filter
noise rejection capability is not modeled with linear equations, a look-up-table is generated 229 229 noise rejection capability is not modeled with linear equations, a look-up-table is generated
for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each 230 230 for multiple filter configurations in which the $C_i$, $D_i$ and $N_i$ parameters are varied: for each
one of these conditions, the low-pass filter rejection defined as the mean power between 231 231 one of these conditions, the low-pass filter rejection defined as the mean power between
half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response 232 232 half the Nyquist frequency and the Nyquist frequency is stored as computed by the frequency response
of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum 233 233 of the digital filter (Fig. \ref{noise-rejection}). An intuitive analysis of this chart hints at an optimum
set of tap length and number of bit for representing the coefficients along the line of the pyramidal 234 234 set of tap length and number of bit for representing the coefficients along the line of the pyramidal
shaped rejection capability function. 235 235 shaped rejection capability function.
236 236
Linear program formalism for solving the problem is well documented: an objective function is 237 237 Linear program formalism for solving the problem is well documented: an objective function is
defined which is linearly dependent on the parameters to be optimized. Constraints are expressed 238 238 defined which is linearly dependent on the parameters to be optimized. Constraints are expressed
as linear equation and solved using one of the available solvers, in our case GLPK\cite{glpk}. 239 239 as linear equation and solved using one of the available solvers, in our case GLPK\cite{glpk}.
With the notation explain in system \ref{model-FIR}, we have defined our linear problem like this: 240 240 With the notation explain in system \ref{model-FIR}, we have defined our linear problem like this:
\paragraph{Variables} 241 241 \paragraph{Variables}
\begin{align*} 242 242 \begin{align*}
x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a given filter} \\ 243 243 x_{i,j} \in \lbrace 0,1 \rbrace & \text{ $i$ is a given filter} \\
& \text{ $j$ is the stage} \\ 244 244 & \text{ $j$ is the stage} \\
& \text{ If $x_{i,j}$ is equal to 1, the filter is selected} \\ 245 245 & \text{ If $x_{i,j}$ is equal to 1, the filter is selected} \\
\end{align*} 246 246 \end{align*}
\paragraph{Constants} 247 247 \paragraph{Constants}
\begin{align*} 248 248 \begin{align*}
\mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\ 249 249 \mathcal{F} = \lbrace F_1 ... F_p \rbrace & \text{ All possible filters}\\
& \text{ $p$ is the number of different filters} \\ 250 250 & \text{ $p$ is the number of different filters} \\
C(i) & \text{ % Constant to let the 251 251 C(i) & \text{ % Constant to let the
number of coefficients %} \\ & \text{ 252 252 number of coefficients %} \\ & \text{
for filter $i$}\\ 253 253 for filter $i$}\\
\pi_C(i) & \text{ % Constant to let the 254 254 \pi_C(i) & \text{ % Constant to let the
number of bits of %}\\ & \text{ 255 255 number of bits of %}\\ & \text{
each coefficient for filter $i$}\\ 256 256 each coefficient for filter $i$}\\
\mathcal{A}_{\max} & \text{ Total space available inside the FPGA} 257 257 \mathcal{A}_{\max} & \text{ Total space available inside the FPGA}
\end{align*} 258 258 \end{align*}
\paragraph{Constraints} 259 259 \paragraph{Constraints}
\begin{align} 260 260 \begin{align}
1 \leq i \leq p & \nonumber\\ 261 261 1 \leq i \leq p & \nonumber\\
1 \leq j \leq q & \text{ $q$ is the max of filter stage} \nonumber \\ 262 262 1 \leq j \leq q & \text{ $q$ is the max of filter stage} \nonumber \\
\forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \nonumber\\ 263 263 \forall j, \mathlarger{\sum_{i}} x_{i,j} = 1 & \text{ At most one filter by stage} \nonumber\\
\mathcal{S}_0 = 0 & \text{ initial occupation} \nonumber\\ 264 264 \mathcal{S}_0 = 0 & \text{ initial occupation} \nonumber\\
\forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{A}_i)} \label{cstr_size} \\ 265 265 \forall j, \mathcal{S}_j = \mathcal{S}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{A}_i)} \label{cstr_size} \\
\mathcal{S} \leq \mathcal{S}_{\max}\nonumber \\ 266 266 \mathcal{S} \leq \mathcal{S}_{\max}\nonumber \\
\mathcal{N}_0 = 0 & \text{ initial rejection}\nonumber\\ 267 267 \mathcal{N}_0 = 0 & \text{ initial rejection}\nonumber\\
\forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{R}_i)} \label{cstr_rejection} \\ 268 268 \forall j, \mathcal{N}_j = \mathcal{N}_{j-1} + \mathlarger{\sum_i (x_{i,j} \times \mathcal{R}_i)} \label{cstr_rejection} \\
\mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\ 269 269 \mathcal{N}_q \geqslant 160 & \text{ an user defined bound}\nonumber\\
& \text{ (e.g. 160~dB here)}\nonumber\\\nonumber 270 270 & \text{ (e.g. 160~dB here)}\nonumber\\\nonumber
\end{align} 271 271 \end{align}
\paragraph{Goal} 272 272 \paragraph{Goal}
\begin{align*} 273 273 \begin{align*}
\min \mathcal{S}_q 274 274 \min \mathcal{S}_q
\end{align*} 275 275 \end{align*}
276 276
The constraint \ref{cstr_size} means the occupation for the current stage $j$ depends on 277 277 The constraint \ref{cstr_size} means the occupation for the current stage $j$ depends on
the previous occupation and the occupation of current selected filter (it is possible 278 278 the previous occupation and the occupation of current selected filter (it is possible
that no filter is selected for this stage). And the second one \ref{cstr_rejection} 279 279 that no filter is selected for this stage). And the second one \ref{cstr_rejection}
means the same thing but for the rejection, the rejection depends the previous rejection 280 280 means the same thing but for the rejection, the rejection depends the previous rejection
plus the rejection of selected filter. 281 281 plus the rejection of selected filter.
282 282
\subsection{Low bandpass ripple and maximum rejection criteria} 283 283 \subsection{Low bandpass ripple and maximum rejection criteria}
284 284
The MILP solver provides a solution to the problem by selecting a series of small FIR with 285 285 The MILP solver provides a solution to the problem by selecting a series of small FIR with
increasing number of bits representing data and coefficients as well as an increasing number 286 286 increasing number of bits representing data and coefficients as well as an increasing number
of coefficients, instead of a single monolithic filter. 287 287 of coefficients, instead of a single monolithic filter.
288 288
\begin{figure}[h!tb] 289 289 \begin{figure}[h!tb]
% \includegraphics[width=\linewidth]{images/compare-fir.pdf} 290 290 % \includegraphics[width=\linewidth]{images/compare-fir.pdf}
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-jmf-light.pdf} 291 291 \includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-jmf-light.pdf}
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 292 292 \caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR
with a cutoff frequency set at half the Nyquist frequency.} 293 293 with a cutoff frequency set at half the Nyquist frequency.}
\label{compare-fir} 294 294 \label{compare-fir}
\end{figure} 295 295 \end{figure}
296 296
Fig. \ref{compare-fir} exhibits the 297 297 Fig. \ref{compare-fir} exhibits the
performance comparison between one solution and a monolithic FIR when selecting a cutoff 298 298 performance comparison between one solution and a monolithic FIR when selecting a cutoff
frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the 299 299 frequency of half the Nyquist frequency: a series of 5 FIR and a series of 10 FIR with the
same space usage are provided as selected by the MILP solver. The FIR cascade provides improved 300 300 same space usage are provided as selected by the MILP solver. The FIR cascade provides improved
rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to 301 301 rejection than the monolithic FIR at the expense of a lower cutoff frequency which remains to
be tuned or compensated for. 302 302 be tuned or compensated for.
303 303
304 304
The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}. 305 305 The resource occupation when synthesizing such FIR on a Xilinx FPGA is summarized as Tab. \ref{t1}.
We have considered a set of resources representative of the hardware platform we work on, 306 306 We have considered a set of resources representative of the hardware platform we work on,
Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on 307 307 Avnet's Zedboard featuring a Xilinx XC7Z020-CLG484-1 Zynq System on Chip (SoC). The results on
Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to 308 308 Tab. \ref{t1} emphasize that implementing the monolithic single FIR is impossible due to
the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10 309 309 the insufficient hardware resources (exhausted LUT resources), while the FIR cascading 5 or 10
filters fit in the available resources. However, in all cases the DSP resources are fully 310 310 filters fit in the available resources. However, in all cases the DSP resources are fully
used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software, 311 311 used: while the design can be synthesized using Xilinx proprietary Vivado 2016.2 software,
implementing the design fails due to the excessive resource usage preventing routing the signals 312 312 implementing the design fails due to the excessive resource usage preventing routing the signals
on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization 313 313 on the FPGA. Such results emphasize on the one hand the improvement prospect of the optimization
procedure by finding non-trivial solutions matching resource constraints, but on the other 314 314 procedure by finding non-trivial solutions matching resource constraints, but on the other
hand also illustrates the limitation of a model with an abstraction layer that does not account 315 315 hand also illustrates the limitation of a model with an abstraction layer that does not account
for the detailed architecture of the hardware. 316 316 for the detailed architecture of the hardware.
317 317
\begin{table}[h!tb] 318 318 \begin{table}[h!tb]
\caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade 319 319 \caption{Resource occupation on a Xilinx Zynq-7000 series FPGA when synthesizing the FIR cascade
identified as optimal by the MILP solver within a finite resource criterion. The last line refers 320 320 identified as optimal by the MILP solver within a finite resource criterion. The last line refers
to available resources on a Zynq-7020 as found on the Zedboard.} 321 321 to available resources on a Zynq-7020 as found on the Zedboard.}
\begin{center} 322 322 \begin{center}
\begin{tabular}{|c|cccc|}\hline 323 323 \begin{tabular}{|c|cccc|}\hline
FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline 324 324 FIR & BlockRAM & LookUpTables & DSP & rejection (dB)\\\hline\hline
1 (monolithic) & 1 & 76183 & 220 & -162 \\ 325 325 1 (monolithic) & 1 & 76183 & 220 & -162 \\
5 & 5 & 18597 & 220 & -160 \\ 326 326 5 & 5 & 18597 & 220 & -160 \\
10 & 8 & 24729 & 220 & -161 \\\hline\hline 327 327 10 & 8 & 24729 & 220 & -161 \\\hline\hline
\textbf{Zynq 7020} & \textbf{420} & \textbf{53200} & \textbf{220} & \\\hline 328 328 \textbf{Zynq 7020} & \textbf{420} & \textbf{53200} & \textbf{220} & \\\hline
%\begin{tabular}{|c|ccccc|}\hline 329 329 %\begin{tabular}{|c|ccccc|}\hline
%FIR & BRAM36 & BRAM18 & LUT & DSP & rejection (dB)\\\hline\hline 330 330 %FIR & BRAM36 & BRAM18 & LUT & DSP & rejection (dB)\\\hline\hline
%1 (monolithic) & 1 & 0 & {\color{Red}76183} & 220 & -162 \\ 331 331 %1 (monolithic) & 1 & 0 & {\color{Red}76183} & 220 & -162 \\
%5 & 0 & 5 & {\color{Green}18597} & 220 & -160 \\ 332 332 %5 & 0 & 5 & {\color{Green}18597} & 220 & -160 \\
%10 & 0 & 8 & {\color{Green}24729} & 220 & -161 \\\hline\hline 333 333 %10 & 0 & 8 & {\color{Green}24729} & 220 & -161 \\\hline\hline
%\textbf{Zynq 7020} & \textbf{140} & \textbf{280} & \textbf{53200} & \textbf{220} & \\\hline 334 334 %\textbf{Zynq 7020} & \textbf{140} & \textbf{280} & \textbf{53200} & \textbf{220} & \\\hline
\end{tabular} 335 335 \end{tabular}
\end{center} 336 336 \end{center}
%\vspace{-0.7cm} 337 337 %\vspace{-0.7cm}
\label{t1} 338 338 \label{t1}
\end{table} 339 339 \end{table}
340 340
\subsection{Alternate criteria}\label{median} 341 341 \subsection{Alternate criteria}\label{median}
342 342
Fig. \ref{compare-fir} provides FIR solutions matching well the targeted transfer 343 343 Fig. \ref{compare-fir} provides FIR solutions matching well the targeted transfer
function, namely low ripple in the bandpass defined as the first 40\% of the frequency 344 344 function, namely low ripple in the bandpass defined as the first 40\% of the frequency
range and maximum rejection of 160~dB in the last 40\% stopband. We illustrate now, for 345 345 range and maximum rejection of 160~dB in the last 40\% stopband. We illustrate now, for
demonstrating the need to properly select the optimization criterion, two cases of poor 346 346 demonstrating the need to properly select the optimization criterion, two cases of poor
filter shapes obtained by selecting the mean value and median value of the rejection, 347 347 filter shapes obtained by selecting the mean value and median value of the rejection,
with no consideration for the ripples in the bandpass. The results of the optimizations, 348 348 with no consideration for the ripples in the bandpass. The results of the optimizations,
in these cases, are shown in Figs. \ref{compare-mean} and \ref{compare-median}. 349 349 in these cases, are shown in Figs. \ref{compare-mean} and \ref{compare-median}.
350 350
\begin{figure}[h!tb] 351 351 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-mean.pdf} 352 352 \includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-mean-light.pdf}
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 353 353 \caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR
with a cutoff frequency set at half the Nyquist frequency.} 354 354 with a cutoff frequency set at half the Nyquist frequency.}
\label{compare-mean} 355 355 \label{compare-mean}
\end{figure} 356 356 \end{figure}
357 357
In the case of the mean value criterion (Fig. \ref{compare-mean}), the solution is not 358 358 In the case of the mean value criterion (Fig. \ref{compare-mean}), the solution is not
acceptable since the notch at the end of the transition band compensates for some unacceptable 359 359 acceptable since the notch at the end of the transition band compensates for some unacceptable
rise in the rejection close to the Nyquist frequency. Applying such a filter might yield excessive 360 360 rise in the rejection close to the Nyquist frequency. Applying such a filter might yield excessive
high frequency spurious components to be aliased at low frequency when decimating the signal. 361 361 high frequency spurious components to be aliased at low frequency when decimating the signal.
Similarly, the lack of criterion on the bandpass shape induces a shape with poor flatness and 362 362 Similarly, the lack of criterion on the bandpass shape induces a shape with poor flatness and
and slowly decaying transfer function starting to attenuate spectral components well before the 363 363 and slowly decaying transfer function starting to attenuate spectral components well before the
transition band starts. Such issues are partly aleviated by replacing a mean rejection value with 364 364 transition band starts. Such issues are partly aleviated by replacing a mean rejection value with
a median rejection value (Fig. \ref{compare-median}) but solutions remain unacceptable for 365 365 a median rejection value (Fig. \ref{compare-median}) but solutions remain unacceptable for
the reasons stated previously and much poorer than those found with the maximum rejection criterion 366 366 the reasons stated previously and much poorer than those found with the maximum rejection criterion
selected earlier (Fig. \ref{compare-fir}). 367 367 selected earlier (Fig. \ref{compare-fir}).
368 368
\begin{figure}[h!tb] 369 369 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-median.pdf} 370 370 \includegraphics[width=\linewidth]{images/fir-mono-vs-fir-series-noise-fixe-median-light.pdf}
\caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR 371 371 \caption{Comparison of the rejection capability between a series of FIR and a monolithic FIR
with a cutoff frequency set at half the Nyquist frequency.} 372 372 with a cutoff frequency set at half the Nyquist frequency.}
\label{compare-median} 373 373 \label{compare-median}
\end{figure} 374 374 \end{figure}
375 375
\section{Filter coefficient selection} 376 376 \section{Filter coefficient selection}
377 377
The coefficients of a single monolithic filter are computed as the impulse response 378 378 The coefficients of a single monolithic filter are computed as the impulse response
of the filter transfer function, and practically approximated by a multitude of methods 379 379 of the filter transfer function, and practically approximated by a multitude of methods
including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing 380 380 including least square optimization (Matlab's {\tt firls} function), Hamming or Kaiser windowing
(Matlab's {\tt fir1} function). 381 381 (Matlab's {\tt fir1} function).
382 382
\begin{figure}[h!tb] 383 383 \begin{figure}[h!tb]
\includegraphics[width=\linewidth]{images/fir1-vs-firls} 384 384 \includegraphics[width=\linewidth]{images/fir1-vs-firls}
\caption{Evolution of the rejection capability of least-square optimized filters and Hamming 385 385 \caption{Evolution of the rejection capability of least-square optimized filters and Hamming
FIR filters as a function of the number of coefficients, for floating point numbers and 8-bit 386 386 FIR filters as a function of the number of coefficients, for floating point numbers and 8-bit
encoded integers.} 387 387 encoded integers.}
\label{2} 388 388 \label{2}
\end{figure} 389 389 \end{figure}
390 390
Cascading filters opens a new optimization opportunity by 391 391 Cascading filters opens a new optimization opportunity by
selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2} 392 392 selecting various coefficient sets depending on the number of coefficients. Fig. \ref{2}
illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better 393 393 illustrates that for a number of coefficients ranging from 8 to 47, {\tt fir1} provides a better
rejection than {\tt firls}: since the linear solver increases the number of coefficients along 394 394 rejection than {\tt firls}: since the linear solver increases the number of coefficients along
the processing chain, the type of selected filter also changes depending on the number of coefficients 395 395 the processing chain, the type of selected filter also changes depending on the number of coefficients
and evolves along the processing chain. 396 396 and evolves along the processing chain.
397 397
\section{Conclusion} 398 398 \section{Conclusion}
399 399
We address the optimization problem of designing a low-pass filter chain in a Field Programmable Gate 400 400 We address the optimization problem of designing a low-pass filter chain in a Field Programmable Gate
Array for improved noise rejection within constrained resource occupation, as needed for 401 401 Array for improved noise rejection within constrained resource occupation, as needed for
real time processing of radiofrequency signal when characterizing spectral phase noise 402 402 real time processing of radiofrequency signal when characterizing spectral phase noise
characteristics of stable oscillators. The flexibility of the digital approach makes the result 403 403 characteristics of stable oscillators. The flexibility of the digital approach makes the result
best suited for closing the loop and using the measurement output in a feedback loop for 404 404 best suited for closing the loop and using the measurement output in a feedback loop for
controlling clocks, e.g. in a quartz-stabilized high performance clock whose long term behavior 405 405 controlling clocks, e.g. in a quartz-stabilized high performance clock whose long term behavior
is controlled by non-piezoelectric resonator (sapphire resonator, microwave or optical 406 406 is controlled by non-piezoelectric resonator (sapphire resonator, microwave or optical
atomic transition). 407 407 atomic transition).
408 408
\section*{Acknowledgement} 409 409 \section*{Acknowledgement}
410 410
This work is supported by the ANR Programme d'Investissement d'Avenir in 411 411 This work is supported by the ANR Programme d'Investissement d'Avenir in
progress at the Time and Frequency Departments of the FEMTO-ST Institute 412 412 progress at the Time and Frequency Departments of the FEMTO-ST Institute
(Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e. 413 413 (Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e.
The authors would like to thank E. Rubiola, F. Vernotte, G. Cabodevila for support and 414 414 The authors would like to thank E. Rubiola, F. Vernotte, G. Cabodevila for support and
fruitful discussions. 415 415 fruitful discussions.
416 416
\bibliographystyle{IEEEtran} 417 417 \bibliographystyle{IEEEtran}
\balance 418 418 \balance
\bibliography{references,biblio} 419 419 \bibliography{references,biblio}
\end{document} 420 420 \end{document}
421 421
\section{Contexte d'ordonnancement} 422 422 \section{Contexte d'ordonnancement}
Dans cette partie, nous donnerons des d\'efinitions de termes rattach\'es au domaine de l'ordonnancement 423 423 Dans cette partie, nous donnerons des d\'efinitions de termes rattach\'es au domaine de l'ordonnancement
et nous verrons que le sujet trait\'e se rapproche beaucoup d'un problème d'ordonnancement. De ce fait 424 424 et nous verrons que le sujet trait\'e se rapproche beaucoup d'un problème d'ordonnancement. De ce fait
nous pourrons aller plus loin que les travaux vus pr\'ec\'edemment et nous tenterons des approches d'ordonnancement 425 425 nous pourrons aller plus loin que les travaux vus pr\'ec\'edemment et nous tenterons des approches d'ordonnancement
et d'optimisation. 426 426 et d'optimisation.
427 427
\subsection{D\'efinition du vocabulaire} 428 428 \subsection{D\'efinition du vocabulaire}
Avant tout, il faut d\'efinir ce qu'est un problème d'optimisation. Il y a deux d\'efinitions 429 429 Avant tout, il faut d\'efinir ce qu'est un problème d'optimisation. Il y a deux d\'efinitions
importantes à donner. La première est propos\'ee par Legrand et Robert dans leur livre \cite{def1-ordo} : 430 430 importantes à donner. La première est propos\'ee par Legrand et Robert dans leur livre \cite{def1-ordo} :
\begin{definition} 431 431 \begin{definition}
\label{def-ordo1} 432 432 \label{def-ordo1}
Un ordonnancement d'un système de t\^aches $G\ =\ (V,\ E,\ w)$ est une fonction $\sigma$ : 433 433 Un ordonnancement d'un système de t\^aches $G\ =\ (V,\ E,\ w)$ est une fonction $\sigma$ :
$V \rightarrow \mathbb{N}$ telle que $\sigma(u) + w(u) \leq \sigma(v)$ pour toute arête $(u,\ v) \in E$. 434 434 $V \rightarrow \mathbb{N}$ telle que $\sigma(u) + w(u) \leq \sigma(v)$ pour toute arête $(u,\ v) \in E$.
\end{definition} 435 435 \end{definition}
436 436
Dit plus simplement, l'ensemble $V$ repr\'esente les t\^aches à ex\'ecuter, l'ensemble $E$ repr\'esente les d\'ependances 437 437 Dit plus simplement, l'ensemble $V$ repr\'esente les t\^aches à ex\'ecuter, l'ensemble $E$ repr\'esente les d\'ependances
des t\^aches et $w$ les temps d'ex\'ecution de la t\^ache. La fonction $\sigma$ donne donc l'heure de d\'ebut de 438 438 des t\^aches et $w$ les temps d'ex\'ecution de la t\^ache. La fonction $\sigma$ donne donc l'heure de d\'ebut de
chacune des t\^aches. La d\'efinition dit que si une t\^ache $v$ d\'epend d'une t\^ache $u$ alors 439 439 chacune des t\^aches. La d\'efinition dit que si une t\^ache $v$ d\'epend d'une t\^ache $u$ alors
la date de d\'ebut de $v$ sera plus grande ou \'egale au d\'ebut de l'ex\'ecution de la t\^ache $u$ plus son 440 440 la date de d\'ebut de $v$ sera plus grande ou \'egale au d\'ebut de l'ex\'ecution de la t\^ache $u$ plus son
temps d'ex\'ecution. 441 441 temps d'ex\'ecution.
442 442
Une autre d\'efinition importante qui est propos\'ee par Leung et al. \cite{def2-ordo} est : 443 443 Une autre d\'efinition importante qui est propos\'ee par Leung et al. \cite{def2-ordo} est :
\begin{definition} 444 444 \begin{definition}
\label{def-ordo2} 445 445 \label{def-ordo2}
L'ordonnancement traite de l'allocation de ressources rares à des activit\'es avec 446 446 L'ordonnancement traite de l'allocation de ressources rares à des activit\'es avec
l'objectif d'optimiser un ou plusieurs critères de performance. 447 447 l'objectif d'optimiser un ou plusieurs critères de performance.
\end{definition} 448 448 \end{definition}
449 449
Cette d\'efinition est plus g\'en\'erique mais elle nous int\'eresse d'avantage que la d\'efinition \ref{def-ordo1}. 450 450 Cette d\'efinition est plus g\'en\'erique mais elle nous int\'eresse d'avantage que la d\'efinition \ref{def-ordo1}.
En effet, la partie qui nous int\'eresse dans cette première d\'efinition est le respect de la pr\'ec\'edance des t\^aches. 451 451 En effet, la partie qui nous int\'eresse dans cette première d\'efinition est le respect de la pr\'ec\'edance des t\^aches.
Dans les faits les dates de d\'ebut ne nous int\'eressent pas r\'eellement. 452 452 Dans les faits les dates de d\'ebut ne nous int\'eressent pas r\'eellement.
453 453
En revanche la d\'efinition \ref{def-ordo2} sera au c\oe{}ur du projet. Pour se convaincre de cela, 454 454 En revanche la d\'efinition \ref{def-ordo2} sera au c\oe{}ur du projet. Pour se convaincre de cela,
il nous faut d'abord d\'efinir quel est le type de problème d'ordonnancement qu'on traite et quelles 455 455 il nous faut d'abord d\'efinir quel est le type de problème d'ordonnancement qu'on traite et quelles
sont les m\'ethodes qu'on peut appliquer. 456 456 sont les m\'ethodes qu'on peut appliquer.
457 457
Les problèmes d'ordonnancement peuvent être class\'es en diff\'erentes cat\'egories : 458 458 Les problèmes d'ordonnancement peuvent être class\'es en diff\'erentes cat\'egories :
\begin{itemize} 459 459 \begin{itemize}
\item T\^aches ind\'ependantes : dans cette cat\'egorie de problèmes, les t\^aches sont complètement ind\'ependantes 460 460 \item T\^aches ind\'ependantes : dans cette cat\'egorie de problèmes, les t\^aches sont complètement ind\'ependantes
les unes des autres. Dans notre cas, ce n'est pas le plus adapt\'e. 461 461 les unes des autres. Dans notre cas, ce n'est pas le plus adapt\'e.
\item Graphe de t\^aches : la d\'efinition \ref{def-ordo1} d\'ecrit cette cat\'egorie. La plupart du temps, 462 462 \item Graphe de t\^aches : la d\'efinition \ref{def-ordo1} d\'ecrit cette cat\'egorie. La plupart du temps,
les t\^aches sont repr\'esent\'ees par une DAG. Cette cat\'egorie est très proche de notre cas puisque nous devons \'egalement ex\'ecuter 463 463 les t\^aches sont repr\'esent\'ees par une DAG. Cette cat\'egorie est très proche de notre cas puisque nous devons \'egalement ex\'ecuter
des t\^aches qui ont un certain nombre de d\'ependances. On pourra même dire que dans certain cas, 464 464 des t\^aches qui ont un certain nombre de d\'ependances. On pourra même dire que dans certain cas,
on a des anti-arbres, c'est à dire que nous avons une multitude de t\^aches d'entr\'ees qui convergent vers une 465 465 on a des anti-arbres, c'est à dire que nous avons une multitude de t\^aches d'entr\'ees qui convergent vers une
t\^ache de fin. 466 466 t\^ache de fin.
\item Workflow : cette cat\'egorie est une sous cat\'egorie des graphes de t\^aches dans le sens où 467 467 \item Workflow : cette cat\'egorie est une sous cat\'egorie des graphes de t\^aches dans le sens où
il s'agit d'un graphe de t\^aches r\'ep\'et\'e de nombreuses de fois. C'est exactement ce type de problème 468 468 il s'agit d'un graphe de t\^aches r\'ep\'et\'e de nombreuses de fois. C'est exactement ce type de problème
que nous traitons ici. 469 469 que nous traitons ici.
\end{itemize} 470 470 \end{itemize}
471 471
Bien entendu, cette liste n'est pas exhaustive et il existe de nombreuses autres classifications et sous-classifications 472 472 Bien entendu, cette liste n'est pas exhaustive et il existe de nombreuses autres classifications et sous-classifications
de ces problèmes. Nous n'avons parl\'e ici que des cat\'egories les plus communes. 473 473 de ces problèmes. Nous n'avons parl\'e ici que des cat\'egories les plus communes.
474 474
Un autre point à d\'efinir, est le critère d'optimisation. Il y a là encore un grand nombre de 475 475 Un autre point à d\'efinir, est le critère d'optimisation. Il y a là encore un grand nombre de
critères possibles. Nous allons donc parler des principaux : 476 476 critères possibles. Nous allons donc parler des principaux :
\begin{itemize} 477 477 \begin{itemize}
\item Temps de compl\'etion total (ou Makespan en anglais) : ce critère est l'un des critères d'optimisation 478 478 \item Temps de compl\'etion total (ou Makespan en anglais) : ce critère est l'un des critères d'optimisation
les plus courant. Il s'agit donc de minimiser la date de fin de la dernière t\^ache de l'ensemble des 479 479 les plus courant. Il s'agit donc de minimiser la date de fin de la dernière t\^ache de l'ensemble des
t\^aches à ex\'ecuter. L'enjeu de cette optimisation est donc de trouver l'ordonnancement optimal permettant 480 480 t\^aches à ex\'ecuter. L'enjeu de cette optimisation est donc de trouver l'ordonnancement optimal permettant
la fin d'ex\'ecution au plus tôt. 481 481 la fin d'ex\'ecution au plus tôt.
\item Somme des temps d'ex\'ecution (Flowtime en anglais) : il s'agit de faire la somme des temps d'ex\'ecution de toutes les t\^aches 482 482 \item Somme des temps d'ex\'ecution (Flowtime en anglais) : il s'agit de faire la somme des temps d'ex\'ecution de toutes les t\^aches
et d'optimiser ce r\'esultat. 483 483 et d'optimiser ce r\'esultat.
\item Le d\'ebit : ce critère quant à lui, vise à augmenter au maximum le d\'ebit de traitement des donn\'ees. 484 484 \item Le d\'ebit : ce critère quant à lui, vise à augmenter au maximum le d\'ebit de traitement des donn\'ees.
\end{itemize} 485 485 \end{itemize}
486 486
En plus de cela, on peut avoir besoin de plusieurs critères d'optimisation. Il s'agit dans ce cas d'une optimisation 487 487 En plus de cela, on peut avoir besoin de plusieurs critères d'optimisation. Il s'agit dans ce cas d'une optimisation
multi-critères. Bien entendu, cela complexifie d'autant plus le problème car la solution la plus optimale pour un 488 488 multi-critères. Bien entendu, cela complexifie d'autant plus le problème car la solution la plus optimale pour un
des critères peut être très mauvaise pour un autre critère. De ce cas, il s'agira de trouver une solution qui permet 489 489 des critères peut être très mauvaise pour un autre critère. De ce cas, il s'agira de trouver une solution qui permet
de faire le meilleur compromis entre tous les critères. 490 490 de faire le meilleur compromis entre tous les critères.
491 491
\subsection{Formalisation du problème} 492 492 \subsection{Formalisation du problème}
\label{formalisation} 493 493 \label{formalisation}
Maintenant que nous avons donn\'e le vocabulaire li\'e à l'ordonnancement, nous allons pouvoir essayer caract\'eriser 494 494 Maintenant que nous avons donn\'e le vocabulaire li\'e à l'ordonnancement, nous allons pouvoir essayer caract\'eriser
formellement notre problème. En effet, nous allons reprendre les contraintes \'enonc\'ees dans la sections \ref{def-contraintes} 495 495 formellement notre problème. En effet, nous allons reprendre les contraintes \'enonc\'ees dans la sections \ref{def-contraintes}
et nous essayerons de les formaliser le plus finement possible. 496 496 et nous essayerons de les formaliser le plus finement possible.
497 497
Comme nous l'avons dit, une t\^ache est un bloc de traitement. Chaque t\^ache $i$ dispose d'un ensemble de paramètres 498 498 Comme nous l'avons dit, une t\^ache est un bloc de traitement. Chaque t\^ache $i$ dispose d'un ensemble de paramètres
que nous nommerons $\mathcal{P}_{i}$. Cet ensemble $\mathcal{P}_i$ est propre à chaque t\^ache et il variera d'une 499 499 que nous nommerons $\mathcal{P}_{i}$. Cet ensemble $\mathcal{P}_i$ est propre à chaque t\^ache et il variera d'une
t\^ache à l'autre. Nous reviendrons plus tard sur les paramètres qui peuvent composer cet ensemble. 500 500 t\^ache à l'autre. Nous reviendrons plus tard sur les paramètres qui peuvent composer cet ensemble.
501 501
Outre cet ensemble $\mathcal{P}_i$, chaque t\^ache dispose de paramètres communs : 502 502 Outre cet ensemble $\mathcal{P}_i$, chaque t\^ache dispose de paramètres communs :
\begin{itemize} 503 503 \begin{itemize}
\item Dur\'ee de la t\^ache : Comme nous l'avons dit auparavant, dans le cadre d'un FPGA le temps est compt\'e en nombre de coup d'horloge. 504 504 \item Dur\'ee de la t\^ache : Comme nous l'avons dit auparavant, dans le cadre d'un FPGA le temps est compt\'e en nombre de coup d'horloge.
En outre, les blocs sont toujours sollicit\'es, certains même sont capables de lire et de renvoyer une r\'esultat à chaque coups d'horloge. 505 505 En outre, les blocs sont toujours sollicit\'es, certains même sont capables de lire et de renvoyer une r\'esultat à chaque coups d'horloge.
Donc la dur\'ee d'une t\^ache ne peut être le laps de temps entre l'entr\'ee d'une donn\'ee et la sortie d'une autre. Nous d\'efinirons la 506 506 Donc la dur\'ee d'une t\^ache ne peut être le laps de temps entre l'entr\'ee d'une donn\'ee et la sortie d'une autre. Nous d\'efinirons la
dur\'ee comme le temps de traitement d'une donn\'ee, c'est à dire la diff\'erence de temps entre la date de sortie d'une donn\'ee 507 507 dur\'ee comme le temps de traitement d'une donn\'ee, c'est à dire la diff\'erence de temps entre la date de sortie d'une donn\'ee
et de sa date d'entr\'ee. Nous nommerons cette dur\'ee $\delta_i$. % Je devrais la nomm\'ee w comme dans la def2 508 508 et de sa date d'entr\'ee. Nous nommerons cette dur\'ee $\delta_i$. % Je devrais la nomm\'ee w comme dans la def2
\item La pr\'ecision : La pr\'ecision d'une donn\'ee est le nombre de bits significatifs qu'elle compte. En effet, au fil des traitements 509 509 \item La pr\'ecision : La pr\'ecision d'une donn\'ee est le nombre de bits significatifs qu'elle compte. En effet, au fil des traitements
les pr\'ecisions peuvent varier. On nomme donc la pr\'ecision d'entr\'ee d'une t\^ache $i$ comme $\pi_i^-$ et la pr\'ecision en sortie $\pi_i^+$. 510 510 les pr\'ecisions peuvent varier. On nomme donc la pr\'ecision d'entr\'ee d'une t\^ache $i$ comme $\pi_i^-$ et la pr\'ecision en sortie $\pi_i^+$.
\item La fr\'equence du flux en entr\'ee (ou sortie) : Cette fr\'equence repr\'esente la fr\'equence des donn\'ees qui arrivent (resp. sortent). 511 511 \item La fr\'equence du flux en entr\'ee (ou sortie) : Cette fr\'equence repr\'esente la fr\'equence des donn\'ees qui arrivent (resp. sortent).
Selon les t\^aches, les fr\'equences varieront. En effet, certains blocs ralentissent le flux c'est pourquoi on distingue la fr\'equence du 512 512 Selon les t\^aches, les fr\'equences varieront. En effet, certains blocs ralentissent le flux c'est pourquoi on distingue la fr\'equence du
flux en entr\'ee et la fr\'equence en sortie. Nous nommerons donc la fr\'equence du flux en entr\'ee $f_i^-$ et la fr\'equence en sortie $f_i^+$. 513 513 flux en entr\'ee et la fr\'equence en sortie. Nous nommerons donc la fr\'equence du flux en entr\'ee $f_i^-$ et la fr\'equence en sortie $f_i^+$.
\item La quantit\'e de donn\'ees en entr\'ee (ou en sortie) : Il s'agit de la quantit\'e de donn\'ees que le bloc s'attend à traiter (resp. 514 514 \item La quantit\'e de donn\'ees en entr\'ee (ou en sortie) : Il s'agit de la quantit\'e de donn\'ees que le bloc s'attend à traiter (resp.
est capable de produire). Les t\^aches peuvent avoir à traiter des gros volumes de donn\'ees et n'en ressortir qu'une partie. Cette 515 515 est capable de produire). Les t\^aches peuvent avoir à traiter des gros volumes de donn\'ees et n'en ressortir qu'une partie. Cette
fois encore, il nous faut donc diff\'erencier l'entr\'ee et la sortie. Nous nommerons donc la quantit\'e de donn\'ees entrantes $q_i^-$ 516 516 fois encore, il nous faut donc diff\'erencier l'entr\'ee et la sortie. Nous nommerons donc la quantit\'e de donn\'ees entrantes $q_i^-$
et la quantit\'e de donn\'ees sortantes $q_i^+$ pour une t\^ache $i$. 517 517 et la quantit\'e de donn\'ees sortantes $q_i^+$ pour une t\^ache $i$.
\item Le d\'ebit d'entr\'ee (ou de sortie) : Ce paramètre correspond au d\'ebit de donn\'ees que la t\^ache est capable de traiter ou qu'elle 518 518 \item Le d\'ebit d'entr\'ee (ou de sortie) : Ce paramètre correspond au d\'ebit de donn\'ees que la t\^ache est capable de traiter ou qu'elle
fournit en sortie. Il s'agit simplement de l'expression des deux pr\'ec\'edents paramètres. Nous d\'efinirons donc la d\'ebit entrant de la 519 519 fournit en sortie. Il s'agit simplement de l'expression des deux pr\'ec\'edents paramètres. Nous d\'efinirons donc la d\'ebit entrant de la
t\^ache $i$ comme $d_i^-\ =\ q_i^-\ *\ f_i^-$ et le d\'ebit sortant comme $d_i^+\ =\ q_i^+\ *\ f_i^+$. 520 520 t\^ache $i$ comme $d_i^-\ =\ q_i^-\ *\ f_i^-$ et le d\'ebit sortant comme $d_i^+\ =\ q_i^+\ *\ f_i^+$.
\item La taille de la t\^ache : La taille dans les FPGA \'etant limit\'ee, ce paramètre exprime donc la place qu'occupe la t\^ache au sein du bloc. 521 521 \item La taille de la t\^ache : La taille dans les FPGA \'etant limit\'ee, ce paramètre exprime donc la place qu'occupe la t\^ache au sein du bloc.
Nous nommerons $\mathcal{A}_i$ cette taille. 522 522 Nous nommerons $\mathcal{A}_i$ cette taille.
\item Les pr\'ed\'ecesseurs et successeurs d'une t\^ache : cela nous permet de connaître les t\^aches requises pour pouvoir traiter 523 523 \item Les pr\'ed\'ecesseurs et successeurs d'une t\^ache : cela nous permet de connaître les t\^aches requises pour pouvoir traiter
la t\^ache $i$ ainsi que les t\^aches qui en d\'ependent. Ces ensemble sont not\'es $\Gamma _i ^-$ et $ \Gamma _i ^+$ \\ 524 524 la t\^ache $i$ ainsi que les t\^aches qui en d\'ependent. Ces ensemble sont not\'es $\Gamma _i ^-$ et $ \Gamma _i ^+$ \\
%TODO Est-ce vraiment un paramètre ? 525 525 %TODO Est-ce vraiment un paramètre ?
\end{itemize} 526 526 \end{itemize}
527 527
Ces diff\'erents paramètres communs sont fortement li\'es aux \'el\'ements de $\mathcal{P}_i$. Voici quelques exemples de relations 528 528 Ces diff\'erents paramètres communs sont fortement li\'es aux \'el\'ements de $\mathcal{P}_i$. Voici quelques exemples de relations
que nous avons identifi\'ees : 529 529 que nous avons identifi\'ees :
\begin{itemize} 530 530 \begin{itemize}
\item $ \delta _i ^+ \ = \ \mathcal{F}_{\delta}(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+,\ \mathcal{P}_i) $ donne le temps d'ex\'ecution 531 531 \item $ \delta _i ^+ \ = \ \mathcal{F}_{\delta}(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+,\ \mathcal{P}_i) $ donne le temps d'ex\'ecution
de la t\^ache en fonction de la pr\'ecision voulue, du d\'ebit et des paramètres internes. 532 532 de la t\^ache en fonction de la pr\'ecision voulue, du d\'ebit et des paramètres internes.
\item $ \pi _i ^+ \ = \ \mathcal{F}_{p}(\pi_i^-,\ \mathcal{P}_i) $, la fonction $F_p$ donne la pr\'ecision en sortie selon la pr\'ecision de d\'epart 533 533 \item $ \pi _i ^+ \ = \ \mathcal{F}_{p}(\pi_i^-,\ \mathcal{P}_i) $, la fonction $F_p$ donne la pr\'ecision en sortie selon la pr\'ecision de d\'epart
et les paramètres internes de la t\^ache. 534 534 et les paramètres internes de la t\^ache.
\item $d_i^+\ =\ \mathcal{F}_d(d_i^-, \mathcal{P}_i)$, la fonction $F_d$ donne le d\'ebit sortant de la t\^ache en fonction du d\'ebit 535 535 \item $d_i^+\ =\ \mathcal{F}_d(d_i^-, \mathcal{P}_i)$, la fonction $F_d$ donne le d\'ebit sortant de la t\^ache en fonction du d\'ebit
sortant et des variables internes de la t\^ache. 536 536 sortant et des variables internes de la t\^ache.
\item $A_i^+\ =\ \mathcal{F}_A(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+, \mathcal{P}_i)$ 537 537 \item $A_i^+\ =\ \mathcal{F}_A(\pi_i^-,\ \pi_i^+,\ d_i^-,\ d_i^+, \mathcal{P}_i)$
\end{itemize} 538 538 \end{itemize}
Pour le moment, nous ne sommes pas capables de donner une d\'efinition g\'en\'erale de ces fonctions. Mais en revanche, 539 539 Pour le moment, nous ne sommes pas capables de donner une d\'efinition g\'en\'erale de ces fonctions. Mais en revanche,
sur quelques exemples simples (cf. \ref{def-contraintes}), nous parvenons à donner une \'evaluation de ces fonctions. 540 540 sur quelques exemples simples (cf. \ref{def-contraintes}), nous parvenons à donner une \'evaluation de ces fonctions.
541 541
Maintenant que nous avons donn\'e toutes les notations utiles, nous allons \'enoncer des contraintes relatives à notre problème. Soit 542 542 Maintenant que nous avons donn\'e toutes les notations utiles, nous allons \'enoncer des contraintes relatives à notre problème. Soit
un DGA $G(V,\ E)$, on a pour toutes arêtes $(i, j)\ \in\ E$ les in\'equations suivantes : 543 543 un DGA $G(V,\ E)$, on a pour toutes arêtes $(i, j)\ \in\ E$ les in\'equations suivantes :
544 544
\paragraph{Contrainte de pr\'ecision :} 545 545 \paragraph{Contrainte de pr\'ecision :}
Cette in\'equation traduit la contrainte de pr\'ecision d'une t\^ache à l'autre : 546 546 Cette in\'equation traduit la contrainte de pr\'ecision d'une t\^ache à l'autre :
\begin{align*} 547 547 \begin{align*}
\pi _i ^+ \geq \pi _j ^- 548 548 \pi _i ^+ \geq \pi _j ^-
\end{align*} 549 549 \end{align*}
550 550
\paragraph{Contrainte de d\'ebit :} 551 551 \paragraph{Contrainte de d\'ebit :}
Cette in\'equation traduit la contrainte de d\'ebit d'une t\^ache à l'autre : 552 552 Cette in\'equation traduit la contrainte de d\'ebit d'une t\^ache à l'autre :
\begin{align*} 553 553 \begin{align*}
d _i ^+ = q _j ^- * (f_i + (1 / s_j) ) & \text{ où } s_j \text{ est une valeur positive de temporisation de la t\^ache} 554 554 d _i ^+ = q _j ^- * (f_i + (1 / s_j) ) & \text{ où } s_j \text{ est une valeur positive de temporisation de la t\^ache}
\end{align*} 555 555 \end{align*}
556 556
\paragraph{Contrainte de synchronisation :} 557 557 \paragraph{Contrainte de synchronisation :}
Il s'agit de la contrainte qui impose que si à un moment du traitement, le DAG se s\'epare en plusieurs branches parallèles 558 558 Il s'agit de la contrainte qui impose que si à un moment du traitement, le DAG se s\'epare en plusieurs branches parallèles
et qu'elles se rejoignent plus tard, la somme des latences sur chacune des branches soit la même. 559 559 et qu'elles se rejoignent plus tard, la somme des latences sur chacune des branches soit la même.
Plus formellement, s'il existe plusieurs chemins disjoints, partant de la t\^ache $s$ et allant à la t\^ache de $f$ alors : 560 560 Plus formellement, s'il existe plusieurs chemins disjoints, partant de la t\^ache $s$ et allant à la t\^ache de $f$ alors :
\begin{align*} 561 561 \begin{align*}
\forall \text{ chemin } \mathcal{C}1(s, .., f), 562 562 \forall \text{ chemin } \mathcal{C}1(s, .., f),
\forall \text{ chemin } \mathcal{C}2(s, .., f) 563 563 \forall \text{ chemin } \mathcal{C}2(s, .., f)
\text{ tel que } \mathcal{C}1 \neq \mathcal{C}2 564 564 \text{ tel que } \mathcal{C}1 \neq \mathcal{C}2
\Rightarrow 565 565 \Rightarrow
\sum _{i} ^{i \in \mathcal{C}1} \delta_i = \sum _{i} ^{i \in \mathcal{C}2} \delta_i 566 566 \sum _{i} ^{i \in \mathcal{C}1} \delta_i = \sum _{i} ^{i \in \mathcal{C}2} \delta_i
\end{align*} 567 567 \end{align*}
568 568
\paragraph{Contrainte de place :} 569 569 \paragraph{Contrainte de place :}
Cette in\'equation traduit la contrainte de place dans le FPGA. La taille max de la puce FPGA est nomm\'e $\mathcal{A}_{FPGA}$ : 570 570 Cette in\'equation traduit la contrainte de place dans le FPGA. La taille max de la puce FPGA est nomm\'e $\mathcal{A}_{FPGA}$ :
\begin{align*} 571 571 \begin{align*}
\sum ^{\text{t\^ache } i} \mathcal{A}_i \leq \mathcal{A}_{FPGA} 572 572 \sum ^{\text{t\^ache } i} \mathcal{A}_i \leq \mathcal{A}_{FPGA}
\end{align*} 573 573 \end{align*}
574 574
\subsection{Exemples de mod\'elisation} 575 575 \subsection{Exemples de mod\'elisation}
\label{exemples-modeles} 576 576 \label{exemples-modeles}
Nous allons maintenant prendre quelques blocs de traitement simples afin d'illustrer au mieux notre modèle. 577 577 Nous allons maintenant prendre quelques blocs de traitement simples afin d'illustrer au mieux notre modèle.
Pour tous nos exemple, nous prendrons un d\'ebit en entr\'ee de 200 Mo/s avec une pr\'ecision de 16 bit. 578 578 Pour tous nos exemple, nous prendrons un d\'ebit en entr\'ee de 200 Mo/s avec une pr\'ecision de 16 bit.
579 579
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