From 76ebb20ed4ea80507784e202091bf80c0113229b Mon Sep 17 00:00:00 2001 From: jmfriedt Date: Fri, 18 May 2018 19:13:42 +0200 Subject: [PATCH] relecture proceeding et corrections : regarder commentaires sur figure et phrase que je ne comprends pas --- ifcs2018_proceeding.tex | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/ifcs2018_proceeding.tex b/ifcs2018_proceeding.tex index 293df9e..09ffff9 100644 --- a/ifcs2018_proceeding.tex +++ b/ifcs2018_proceeding.tex @@ -85,15 +85,17 @@ processor architecture, implementing such a filter on an FPGA offer more degrees not only the coefficient values and number of taps must be defined, but also the number of bits defining the coefficients and the sample size. -Ideally the coefficient are expressed as floating point value but this notation isn't a efficient way to -work with FPGA. Instead we prefer convert this floating point values into integer values. However this -conversion result in some precision loss. Actually as show figure \ref{float_vs_int}, we see that we aren't +The coefficients are classically expressed as floating point values. However, this binary +number representation is not efficient for fast arithmetic computation by an FPGA. Instead, +we select to quantify these floating point values into integer values. This quantization +will result in some precision loss. As illustrated in Fig. \ref{float_vs_int}, we see that we aren't need too coefficients or too sample size. If we have lot of coefficients but a small sample size, the first and last are equal to zero. But if we have too sample size for few coefficients that not improve the quality. +% JMF je ne comprends pas la derniere phrase ci-dessus ni la figure ci dessous \begin{figure}[h!tb] \includegraphics[width=\linewidth]{images/float-vs-integer.pdf} -\caption{Illistration of coefficients choice impact} +\caption{Impact of the quantization resolution of the coefficients} \label{float_vs_int} \end{figure} -- 2.16.4