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biblio.bib
| @thesis{gwen-cogen, | 1 | 1 | @thesis{gwen-cogen, | |
| author = {Gwenhaël Goavec-Merou}, | 2 | 2 | author = {Gwenhaël Goavec-Merou}, | |
| title = {Générateur de coprocesseur pour le traitement de données en flux (vidéo ou similaire) sur {FPGA}}, | 3 | 3 | title = {Générateur de coprocesseur pour le traitement de données en flux (vidéo ou similaire) sur {FPGA}}, | |
| institution = {FEMTO-ST}, | 4 | 4 | institution = {FEMTO-ST}, | |
| year = {2014} | 5 | 5 | year = {2014} | |
| } | 6 | 6 | } | |
| 7 | 7 | |||
| @article{hide, | 8 | 8 | @article{hide, | |
| title={HIDE: A hardware intelligent description environment}, | 9 | 9 | title={HIDE: A hardware intelligent description environment}, | |
| author={Benkrid, Khaled and Belkacemi, S and Benkrid, Abdsamad}, | 10 | 10 | author={Benkrid, Khaled and Belkacemi, S and Benkrid, Abdsamad}, | |
| journal={Microprocessors and Microsystems}, | 11 | 11 | journal={Microprocessors and Microsystems}, | |
| volume={30}, | 12 | 12 | volume={30}, | |
| number={6}, | 13 | 13 | number={6}, | |
| pages={283--300}, | 14 | 14 | pages={283--300}, | |
| year={2006}, | 15 | 15 | year={2006}, | |
| publisher={Elsevier} | 16 | 16 | publisher={Elsevier} | |
| } | 17 | 17 | } | |
| 18 | 18 | |||
| @inproceedings{skeleton, | 19 | 19 | @inproceedings{skeleton, | |
| title={High level programming for {FPGA} based image and video processing using hardware skeletons}, | 20 | 20 | title={High level programming for {FPGA} based image and video processing using hardware skeletons}, | |
| author={Benkrid, Khaled and Crookes, Danny and Smith, J and Benkrid, Abdsamad}, | 21 | 21 | author={Benkrid, Khaled and Crookes, Danny and Smith, J and Benkrid, Abdsamad}, | |
| booktitle={Field-Programmable Custom Computing Machines, 2001. FCCM'01. The 9th Annual IEEE Symposium on}, | 22 | 22 | booktitle={Field-Programmable Custom Computing Machines, 2001. FCCM'01. The 9th Annual IEEE Symposium on}, | |
| pages={219--226}, | 23 | 23 | pages={219--226}, | |
| year={2001}, | 24 | 24 | year={2001}, | |
| organization={IEEE} | 25 | 25 | organization={IEEE} | |
| } | 26 | 26 | } | |
| 27 | 27 | |||
| @article{benkrid2004application, | 28 | 28 | @article{benkrid2004application, | |
| title={From application descriptions to hardware in seconds: a logic-based approach to bridging the gap}, | 29 | 29 | title={From application descriptions to hardware in seconds: a logic-based approach to bridging the gap}, | |
| author={Benkrid, Khaled and Crookes, Danny}, | 30 | 30 | author={Benkrid, Khaled and Crookes, Danny}, | |
| journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, | 31 | 31 | journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, | |
| volume={12}, | 32 | 32 | volume={12}, | |
| number={4}, | 33 | 33 | number={4}, | |
| pages={420--436}, | 34 | 34 | pages={420--436}, | |
| year={2004}, | 35 | 35 | year={2004}, | |
| publisher={IEEE} | 36 | 36 | publisher={IEEE} | |
| } | 37 | 37 | } | |
| 38 | 38 | |||
| @phdthesis{these-dsp-fpga, | 39 | 39 | @phdthesis{these-dsp-fpga, | |
| title={Design methodologies and architectures for digital signal processing on {FPGA}s}, | 40 | 40 | title={Design methodologies and architectures for digital signal processing on {FPGA}s}, | |
| author={Mirzaei, Shahnam}, | 41 | 41 | author={Mirzaei, Shahnam}, | |
| year={2010}, | 42 | 42 | year={2010}, | |
| school={UNIVERSITY OF CALIFORNIA SANTA BARBARA} | 43 | 43 | school={UNIVERSITY OF CALIFORNIA SANTA BARBARA} | |
| } | 44 | 44 | } | |
| 45 | 45 | |||
| @article{def1-ordo, | 46 | 46 | @article{def1-ordo, | |
| title={Algorithmique Parallèle-Cours Et Exercices Corrigés}, | 47 | 47 | title={Algorithmique Parallèle-Cours Et Exercices Corrigés}, | |
| author={Legrand, Arnaud and Robert, Yves}, | 48 | 48 | author={Legrand, Arnaud and Robert, Yves}, | |
| year={2003}, | 49 | 49 | year={2003}, | |
| publisher={Dunod} | 50 | 50 | publisher={Dunod} | |
| } | 51 | 51 | } | |
| 52 | 52 | |||
| @article{these-mathias, | 53 | 53 | @article{these-mathias, | |
| title={Optimisation du débit pour des applications linéaires multi-tâches sur plateformes distribuées incluant des temps de reconfiguration}, | 54 | 54 | title={Optimisation du débit pour des applications linéaires multi-tâches sur plateformes distribuées incluant des temps de reconfiguration}, | |
| author={Coqblin, Mathias}, | 55 | 55 | author={Coqblin, Mathias}, | |
| institution = {FEMTO-ST}, | 56 | 56 | institution = {FEMTO-ST}, | |
| year={2012} | 57 | 57 | year={2012} | |
| } | 58 | 58 | } | |
| 59 | 59 | |||
| @thesis{these-alex, | 60 | 60 | @thesis{these-alex, | |
| author = {Alexandru Dobrila}, | 61 | 61 | author = {Alexandru Dobrila}, | |
| title = {Optimisation du débit en environnement distribué incertain}, | 62 | 62 | title = {Optimisation du débit en environnement distribué incertain}, | |
| institution = {FEMTO-ST}, | 63 | 63 | institution = {FEMTO-ST}, | |
| year = {2011} | 64 | 64 | year = {2011} | |
| } | 65 | 65 | } | |
| 66 | 66 | |||
| @book{def2-ordo, | 67 | 67 | @book{def2-ordo, | |
| title={Handbook of scheduling: algorithms, models, and performance analysis}, | 68 | 68 | title={Handbook of scheduling: algorithms, models, and performance analysis}, | |
| author={Leung, Joseph YT}, | 69 | 69 | author={Leung, Joseph YT}, | |
| year={2004}, | 70 | 70 | year={2004}, | |
| publisher={CRC Press} | 71 | 71 | publisher={CRC Press} | |
| } | 72 | 72 | } | |
| 73 | 73 | |||
| @inproceedings{def-ordo-en-ligne, | 74 | 74 | @inproceedings{def-ordo-en-ligne, | |
| title={On the Definition of "On-Line" in Job Scheduling Problems}, | 75 | 75 | title={On the Definition of "On-Line" in Job Scheduling Problems}, | |
| author={Feitelson, Dror G and Mu'alem, Ahuva W}, | 76 | 76 | author={Feitelson, Dror G and Mu'alem, Ahuva W}, | |
| booktitle={SIGACT NEWS}, | 77 | 77 | booktitle={SIGACT NEWS}, | |
| year={2000}, | 78 | 78 | year={2000}, | |
| organization={Citeseer} | 79 | 79 | organization={Citeseer} | |
| } | 80 | 80 | } | |
| 81 | 81 | |||
| @article{shmueli2005backfilling, | 82 | 82 | @article{shmueli2005backfilling, | |
| title={Backfilling with lookahead to optimize the packing of parallel jobs}, | 83 | 83 | title={Backfilling with lookahead to optimize the packing of parallel jobs}, | |
| author={Shmueli, Edi and Feitelson, Dror G}, | 84 | 84 | author={Shmueli, Edi and Feitelson, Dror G}, | |
| journal={Journal of Parallel and Distributed Computing}, | 85 | 85 | journal={Journal of Parallel and Distributed Computing}, | |
| volume={65}, | 86 | 86 | volume={65}, | |
| number={9}, | 87 | 87 | number={9}, | |
| pages={1090--1107}, | 88 | 88 | pages={1090--1107}, | |
| year={2005}, | 89 | 89 | year={2005}, | |
| publisher={Elsevier} | 90 | 90 | publisher={Elsevier} | |
| } | 91 | 91 | } | |
| 92 | 92 | |||
| @article{graham1979optimization, | 93 | 93 | @article{graham1979optimization, | |
| title={Optimization and approximation in deterministic sequencing and scheduling: a survey}, | 94 | 94 | title={Optimization and approximation in deterministic sequencing and scheduling: a survey}, | |
| author={Graham, Ronald L and Lawler, Eugene L and Lenstra, Jan Karel and Kan, AHG Rinnooy}, | 95 | 95 | author={Graham, Ronald L and Lawler, Eugene L and Lenstra, Jan Karel and Kan, AHG Rinnooy}, | |
| journal={Annals of discrete mathematics}, | 96 | 96 | journal={Annals of discrete mathematics}, | |
| volume={5}, | 97 | 97 | volume={5}, | |
| pages={287--326}, | 98 | 98 | pages={287--326}, | |
| year={1979}, | 99 | 99 | year={1979}, | |
| publisher={Elsevier} | 100 | 100 | publisher={Elsevier} | |
| } | 101 | 101 | } | |
| 102 | 102 | |||
| @article{salvador2012accelerating, | 103 | 103 | @article{salvador2012accelerating, | |
| title={Accelerating {FPGA}-based evolution of wavelet transform filters by optimized task scheduling}, | 104 | 104 | title={Accelerating {FPGA}-based evolution of wavelet transform filters by optimized task scheduling}, | |
| author={Salvador, Ruben and Vidal, Alberto and Moreno, Felix and Riesgo, Teresa and Sekanina, Lukas}, | 105 | 105 | author={Salvador, Ruben and Vidal, Alberto and Moreno, Felix and Riesgo, Teresa and Sekanina, Lukas}, | |
| journal={Microprocessors and Microsystems}, | 106 | 106 | journal={Microprocessors and Microsystems}, | |
| volume={36}, | 107 | 107 | volume={36}, | |
| number={5}, | 108 | 108 | number={5}, | |
| pages={427--438}, | 109 | 109 | pages={427--438}, | |
| year={2012}, | 110 | 110 | year={2012}, | |
| publisher={Elsevier} | 111 | 111 | publisher={Elsevier} | |
| } | 112 | 112 | } | |
| 113 | 113 | |||
| @article{zhuo2007scalable, | 114 | 114 | @article{zhuo2007scalable, | |
| title={Scalable and modular algorithms for floating-point matrix multiplication on reconfigurable computing systems}, | 115 | 115 | title={Scalable and modular algorithms for floating-point matrix multiplication on reconfigurable computing systems}, | |
| author={Zhuo, Ling and Prasanna, Viktor K}, | 116 | 116 | author={Zhuo, Ling and Prasanna, Viktor K}, | |
| journal={Parallel and Distributed Systems, IEEE Transactions on}, | 117 | 117 | journal={Parallel and Distributed Systems, IEEE Transactions on}, | |
| volume={18}, | 118 | 118 | volume={18}, | |
| number={4}, | 119 | 119 | number={4}, | |
| pages={433--448}, | 120 | 120 | pages={433--448}, | |
| year={2007}, | 121 | 121 | year={2007}, | |
| publisher={IEEE} | 122 | 122 | publisher={IEEE} | |
| } | 123 | 123 | } | |
| 124 | 124 | |||
| @article{olariu1993computing, | 125 | 125 | @article{olariu1993computing, | |
| title={Computing the Hough transform on reconfigurable meshes}, | 126 | 126 | title={Computing the Hough transform on reconfigurable meshes}, | |
| author={Olariu, Stephan and Schwing, James L and Zhang, Jingyuan}, | 127 | 127 | author={Olariu, Stephan and Schwing, James L and Zhang, Jingyuan}, | |
| journal={Image and vision computing}, | 128 | 128 | journal={Image and vision computing}, | |
| volume={11}, | 129 | 129 | volume={11}, | |
| number={10}, | 130 | 130 | number={10}, | |
| pages={623--628}, | 131 | 131 | pages={623--628}, | |
| year={1993}, | 132 | 132 | year={1993}, | |
| publisher={Elsevier} | 133 | 133 | publisher={Elsevier} | |
| } | 134 | 134 | } | |
| 135 | 135 | |||
| @article{pan1999improved, | 136 | 136 | @article{pan1999improved, | |
| title={An improved constant-time algorithm for computing the Radon and Hough transforms on a reconfigurable mesh}, | 137 | 137 | title={An improved constant-time algorithm for computing the Radon and Hough transforms on a reconfigurable mesh}, | |
| author={Pan, Yi and Li, Keqin and Hamdi, Mounir}, | 138 | 138 | author={Pan, Yi and Li, Keqin and Hamdi, Mounir}, | |
| journal={Systems, Man and Cybernetics, Part A: Systems and Humans, IEEE Transactions on}, | 139 | 139 | journal={Systems, Man and Cybernetics, Part A: Systems and Humans, IEEE Transactions on}, | |
| volume={29}, | 140 | 140 | volume={29}, | |
| number={4}, | 141 | 141 | number={4}, | |
| pages={417--421}, | 142 | 142 | pages={417--421}, | |
| year={1999}, | 143 | 143 | year={1999}, | |
| publisher={IEEE} | 144 | 144 | publisher={IEEE} | |
| } | 145 | 145 | } | |
| 146 | 146 | |||
| @article{kasbah2008multigrid, | 147 | 147 | @article{kasbah2008multigrid, | |
| title={Multigrid solvers in reconfigurable hardware}, | 148 | 148 | title={Multigrid solvers in reconfigurable hardware}, | |
| author={Kasbah, Safaa J and Damaj, Issam W and Haraty, Ramzi A}, | 149 | 149 | author={Kasbah, Safaa J and Damaj, Issam W and Haraty, Ramzi A}, | |
| journal={Journal of Computational and Applied Mathematics}, | 150 | 150 | journal={Journal of Computational and Applied Mathematics}, | |
| volume={213}, | 151 | 151 | volume={213}, | |
| number={1}, | 152 | 152 | number={1}, | |
| pages={79--94}, | 153 | 153 | pages={79--94}, | |
| year={2008}, | 154 | 154 | year={2008}, | |
| publisher={Elsevier} | 155 | 155 | publisher={Elsevier} | |
| } | 156 | 156 | } | |
| 157 | 157 | |||
| @inproceedings{crookes1998environment, | 158 | 158 | @inproceedings{crookes1998environment, | |
| title={An environment for generating {FPGA} architectures for image algebra-based algorithms}, | 159 | 159 | title={An environment for generating {FPGA} architectures for image algebra-based algorithms}, | |
| author={Crookes, Danny and Alotaibi, Khalid and Bouridane, Ahmed and Donachy, Paul and Benkrid, Abdsamad}, | 160 | 160 | author={Crookes, Danny and Alotaibi, Khalid and Bouridane, Ahmed and Donachy, Paul and Benkrid, Abdsamad}, | |
| booktitle={Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on}, | 161 | 161 | booktitle={Image Processing, 1998. ICIP 98. Proceedings. 1998 International Conference on}, | |
| pages={990--994}, | 162 | 162 | pages={990--994}, | |
| year={1998}, | 163 | 163 | year={1998}, | |
| organization={IEEE} | 164 | 164 | organization={IEEE} | |
| } | 165 | 165 | } | |
| 166 | 166 | |||
| @article{crookes2000design, | 167 | 167 | @article{crookes2000design, | |
| title={Design and implementation of a high level programming environment for {FPGA}-based image processing}, | 168 | 168 | title={Design and implementation of a high level programming environment for {FPGA}-based image processing}, | |
| author={Crookes, D and Benkrid, K and Bouridane, A and Alotaibi, K and Benkrid, A}, | 169 | 169 | author={Crookes, D and Benkrid, K and Bouridane, A and Alotaibi, K and Benkrid, A}, | |
| journal={IEE Proceedings-Vision, Image and Signal Processing}, | 170 | 170 | journal={IEE Proceedings-Vision, Image and Signal Processing}, | |
| volume={147}, | 171 | 171 | volume={147}, | |
| number={4}, | 172 | 172 | number={4}, | |
| pages={377--384}, | 173 | 173 | pages={377--384}, | |
| year={2000}, | 174 | 174 | year={2000}, | |
| publisher={IET} | 175 | 175 | publisher={IET} | |
| } | 176 | 176 | } | |
| 177 | 177 | |||
| @article{benkrid2002towards, | 178 | 178 | @article{benkrid2002towards, | |
| title={Towards a general framework for {FPGA} based image processing using hardware skeletons}, | 179 | 179 | title={Towards a general framework for {FPGA} based image processing using hardware skeletons}, | |
| author={Benkrid, Khaled and Crookes, Danny and Benkrid, Abdsamad}, | 180 | 180 | author={Benkrid, Khaled and Crookes, Danny and Benkrid, Abdsamad}, | |
| journal={Parallel Computing}, | 181 | 181 | journal={Parallel Computing}, | |
| volume={28}, | 182 | 182 | volume={28}, | |
| number={7}, | 183 | 183 | number={7}, | |
| pages={1141--1154}, | 184 | 184 | pages={1141--1154}, | |
| year={2002}, | 185 | 185 | year={2002}, | |
| publisher={Elsevier} | 186 | 186 | publisher={Elsevier} | |
| } | 187 | 187 | } | |
| 188 | 188 | |||
| @article{andrich2018high, | 189 | 189 | @article{andrich2018high, | |
| title={High-Precision Measurement of Sine and Pulse Reference Signals Using Software-Defined Radio}, | 190 | 190 | title={High-Precision Measurement of Sine and Pulse Reference Signals Using Software-Defined Radio}, | |
| author={Andrich, Carsten and Ihlow, Alexander and Bauer, Julia and Beuster, Niklas and Del Galdo, Giovanni}, | 191 | 191 | author={Andrich, Carsten and Ihlow, Alexander and Bauer, Julia and Beuster, Niklas and Del Galdo, Giovanni}, | |
| journal={IEEE Transactions on Instrumentation and Measurement}, | 192 | 192 | journal={IEEE Transactions on Instrumentation and Measurement}, | |
| year={2018}, | 193 | 193 | year={2018}, | |
| publisher={IEEE}, | 194 | 194 | publisher={IEEE}, | |
| pages={1132--1141}, | 195 | 195 | pages={1132--1141}, | |
| volume=67, | 196 | 196 | volume=67, | |
| number=5, | 197 | 197 | number=5, | |
| month={May} | 198 | 198 | month={May} | |
| } | 199 | 199 | } | |
| 200 | ||||
| 201 | @inproceedings{carolina1, | |||
| 202 | title={Digital electronics based on red pitaya platform for coherent fiber links}, | |||
| 203 | author={Olaya, AC Cardenas and Micalizio, S and Ortolano, M and Calosso, CE and Rubiola, E and Friedt, JM}, | |||
| 204 | booktitle={2016 European Frequency and Time Forum (EFTF)}, | |||
| 205 | pages={1--4}, | |||
| 206 | year={2016}, | |||
| 207 | organization={IEEE} | |||
| 208 | } | |||
| 209 | ||||
| 210 | @article{carolina2, |
ifcs2018_journal.tex
| % fusionner max rejection a surface donnee v.s minimiser surface a rejection donnee | 1 | 1 | % fusionner max rejection a surface donnee v.s minimiser surface a rejection donnee | |
| % demontrer comment la quantification rejette du bruit vers les hautes frequences => 6 dB de | 2 | 2 | % demontrer comment la quantification rejette du bruit vers les hautes frequences => 6 dB de | |
| % rejection par bit et perte si moins de bits que rejection/6 | 3 | 3 | % rejection par bit et perte si moins de bits que rejection/6 | |
| % developper programme lineaire en incluant le decalage de bits | 4 | 4 | % developper programme lineaire en incluant le decalage de bits | |
| % insister que avant on etait synthetisable mais pas implementable, alors que maintenant on | 5 | 5 | % insister que avant on etait synthetisable mais pas implementable, alors que maintenant on | |
| % implemente et on demontre que ca tourne | 6 | 6 | % implemente et on demontre que ca tourne | |
| % gwen : pourquoi le FIR est desormais implementable et ne l'etait pas meme sur zedboard->new FIR ? | 7 | 7 | % gwen : pourquoi le FIR est desormais implementable et ne l'etait pas meme sur zedboard->new FIR ? | |
| % Gwen : peut-on faire un vrai banc de bruit de phase avec ce FIR, ie ajouter ADC, NCO et mixer | 8 | 8 | % Gwen : peut-on faire un vrai banc de bruit de phase avec ce FIR, ie ajouter ADC, NCO et mixer | |
| % (zedboard ou redpit) | 9 | 9 | % (zedboard ou redpit) | |
| 10 | 10 | |||
| % ajouter pyramide "juste" | 11 | |||
| % label schema : verifier que "argumenter de la cascade de FIR" est fait | 12 | 11 | % label schema : verifier que "argumenter de la cascade de FIR" est fait | |
| 13 | 12 | |||
| \documentclass[a4paper,conference]{IEEEtran/IEEEtran} | 14 | 13 | \documentclass[a4paper,conference]{IEEEtran/IEEEtran} | |
| \usepackage{graphicx,color,hyperref} | 15 | 14 | \usepackage{graphicx,color,hyperref} | |
| \usepackage{amsfonts} | 16 | 15 | \usepackage{amsfonts} | |
| \usepackage{amsthm} | 17 | 16 | \usepackage{amsthm} | |
| \usepackage{amssymb} | 18 | 17 | \usepackage{amssymb} | |
| \usepackage{amsmath} | 19 | 18 | \usepackage{amsmath} | |
| \usepackage{algorithm2e} | 20 | 19 | \usepackage{algorithm2e} | |
| \usepackage{url,balance} | 21 | 20 | \usepackage{url,balance} | |
| \usepackage[normalem]{ulem} | 22 | 21 | \usepackage[normalem]{ulem} | |
| \usepackage{tikz} | 23 | 22 | \usepackage{tikz} | |
| \usetikzlibrary{positioning,fit} | 24 | 23 | \usetikzlibrary{positioning,fit} | |
| \usepackage{multirow} | 25 | 24 | \usepackage{multirow} | |
| \usepackage{scalefnt} | 26 | 25 | \usepackage{scalefnt} | |
| 27 | 26 | |||
| % correct bad hyphenation here | 28 | 27 | % correct bad hyphenation here | |
| \hyphenation{op-tical net-works semi-conduc-tor} | 29 | 28 | \hyphenation{op-tical net-works semi-conduc-tor} | |
| \textheight=26cm | 30 | 29 | \textheight=26cm | |
| \setlength{\footskip}{30pt} | 31 | 30 | \setlength{\footskip}{30pt} | |
| \pagenumbering{gobble} | 32 | 31 | \pagenumbering{gobble} | |
| \begin{document} | 33 | 32 | \begin{document} | |
| \title{Filter optimization for real time digital processing of radiofrequency signals: application | 34 | 33 | \title{Filter optimization for real time digital processing of radiofrequency signals: application | |
| to oscillator metrology} | 35 | 34 | to oscillator metrology} | |
| 36 | 35 | |||
| \author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2}, | 37 | 36 | \author{\IEEEauthorblockN{A. Hugeat\IEEEauthorrefmark{1}\IEEEauthorrefmark{2}, J. Bernard\IEEEauthorrefmark{2}, | |
| G. Goavec-M\'erou\IEEEauthorrefmark{1}, | 38 | 37 | G. Goavec-M\'erou\IEEEauthorrefmark{1}, | |
| P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}} | 39 | 38 | P.-Y. Bourgeois\IEEEauthorrefmark{1}, J.-M. Friedt\IEEEauthorrefmark{1}} | |
| \IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France } | 40 | 39 | \IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, Time \& Frequency department, Besan\c con, France } | |
| \IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\ | 41 | 40 | \IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Computer Science department DISC, Besan\c con, France \\ | |
| Email: \{pyb2,jmfriedt\}@femto-st.fr} | 42 | 41 | Email: \{pyb2,jmfriedt\}@femto-st.fr} | |
| } | 43 | 42 | } | |
| \maketitle | 44 | 43 | \maketitle | |
| \thispagestyle{plain} | 45 | 44 | \thispagestyle{plain} | |
| \pagestyle{plain} | 46 | 45 | \pagestyle{plain} | |
| \newtheorem{definition}{Definition} | 47 | 46 | \newtheorem{definition}{Definition} | |
| 48 | 47 | |||
| \begin{abstract} | 49 | 48 | \begin{abstract} | |
| Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to | 50 | 49 | Software Defined Radio (SDR) provides stability, flexibility and reconfigurability to | |
| radiofrequency signal processing. Applied to oscillator characterization in the context | 51 | 50 | radiofrequency signal processing. Applied to oscillator characterization in the context | |
| of ultrastable clocks, stringent filtering requirements are defined by spurious signal or | 52 | 51 | of ultrastable clocks, stringent filtering requirements are defined by spurious signal or | |
| noise rejection needs. Since real time radiofrequency processing must be performed in a | 53 | 52 | noise rejection needs. Since real time radiofrequency processing must be performed in a | |
| Field Programmable Array to meet timing constraints, we investigate optimization strategies | 54 | 53 | Field Programmable Array to meet timing constraints, we investigate optimization strategies | |
| to design filters meeting rejection characteristics while limiting the hardware resources | 55 | 54 | to design filters meeting rejection characteristics while limiting the hardware resources | |
| required and keeping timing constraints within the targeted measurement bandwidths. | 56 | 55 | required and keeping timing constraints within the targeted measurement bandwidths. The | |
| 56 | presented technique is applicable to scheduling any sequence of processing blocks characterized | |||
| 57 | by a throughput, resource occupation and performance tabulated as a function of configuration | |||
| 58 | characateristics, as is the case for filters with their coefficients and resolution yielding | |||
| 59 | rejection and number of multipliers. | |||
| \end{abstract} | 57 | 60 | \end{abstract} | |
| 58 | 61 | |||
| \begin{IEEEkeywords} | 59 | 62 | \begin{IEEEkeywords} | |
| Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter | 60 | 63 | Software Defined Radio, Mixed-Integer Linear Programming, Finite Impulse Response filter | |
| \end{IEEEkeywords} | 61 | 64 | \end{IEEEkeywords} | |
| 62 | 65 | |||
| \section{Digital signal processing of ultrastable clock signals} | 63 | 66 | \section{Digital signal processing of ultrastable clock signals} | |
| 64 | 67 | |||
| Analog oscillator phase noise characteristics are classically performed by downconverting | 65 | 68 | Analog oscillator phase noise characteristics are classically performed by downconverting | |
| the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband, | 66 | 69 | the radiofrequency signal using a saturated mixer to bring the radiofrequency signal to baseband, | |
| followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In | 67 | 70 | followed by a Fourier analysis of the beat signal to analyze phase fluctuations close to carrier. In | |
| a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by | 68 | 71 | a fully digital approach, the radiofrequency signal is digitized and numerically downconverted by | |
| multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}. | 69 | 72 | multiplying the samples with a local numerically controlled oscillator (Fig. \ref{schema}) \cite{rsi}. | |
| 70 | 73 | |||
| \begin{figure}[h!tb] | 71 | 74 | \begin{figure}[h!tb] | |
| \begin{center} | 72 | 75 | \begin{center} | |
| \includegraphics[width=.8\linewidth]{images/schema} | 73 | 76 | \includegraphics[width=.8\linewidth]{images/schema} | |
| \end{center} | 74 | 77 | \end{center} | |
| \caption{Fully digital oscillator phase noise characterization: the Device Under Test | 75 | 78 | \caption{Fully digital oscillator phase noise characterization: the Device Under Test | |
| (DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and | 76 | 79 | (DUT) signal is sampled by the radiofrequency grade Analog to Digital Converter (ADC) and | |
| downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals | 77 | 80 | downconverted by mixing with a Numerically Controlled Oscillator (NCO). Unwanted signals | |
| and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite | 78 | 81 | and noise aliases are rejected by a Low Pass Filter (LPF) implemented as a cascade of Finite | |
| Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays | 79 | 82 | Impulse Response (FIR) filters. The signal is then decimated before a Fourier analysis displays | |
| the spectral characteristics of the phase fluctuations.} | 80 | 83 | the spectral characteristics of the phase fluctuations.} | |
| \label{schema} | 81 | 84 | \label{schema} | |
| \end{figure} | 82 | 85 | \end{figure} | |
| 83 | 86 | |||
| As with the analog mixer, | 84 | 87 | As with the analog mixer, | |
| the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as | 85 | 88 | the non-linear behavior of the downconverter introduces noise or spurious signal aliasing as | |
| well as the generation of the frequency sum signal in addition to the frequency difference. | 86 | 89 | well as the generation of the frequency sum signal in addition to the frequency difference. | |
| These unwanted spectral characteristics must be rejected before decimating the data stream | 87 | 90 | These unwanted spectral characteristics must be rejected before decimating the data stream | |
| for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the | 88 | 91 | for the phase noise spectral characterization \cite{andrich2018high}. The characteristics introduced between the | |
| downconverter | 89 | 92 | downconverter | |
| and the decimation processing blocks are core characteristics of an oscillator characterization | 90 | 93 | and the decimation processing blocks are core characteristics of an oscillator characterization | |
| system, and must reject out-of-band signals below the targeted phase noise -- typically in the | 91 | 94 | system, and must reject out-of-band signals below the targeted phase noise -- typically in the | |
| sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will | 92 | 95 | sub -170~dBc/Hz for ultrastable oscillator we aim at characterizing. The filter blocks will | |
| use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency | 93 | 96 | use most resources of the Field Programmable Gate Array (FPGA) used to process the radiofrequency | |
| datastream: optimizing the performance of the filter while reducing the needed resources is | 94 | 97 | datastream: optimizing the performance of the filter while reducing the needed resources is | |
| hence tackled in a systematic approach using optimization techniques. Most significantly, we | 95 | 98 | hence tackled in a systematic approach using optimization techniques. Most significantly, we | |
| tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with | 96 | 99 | tackle the issue by attempting to cascade multiple Finite Impulse Response (FIR) filters with | |
| tunable number of coefficients and tunable number of bits representing the coefficients and the | 97 | 100 | tunable number of coefficients and tunable number of bits representing the coefficients and the | |
| data being processed. | 98 | 101 | data being processed. | |
| 99 | 102 | |||
| \section{Finite impulse response filter} | 100 | 103 | \section{Finite impulse response filter} | |
| 101 | 104 | |||
| We select FIR filter for their unconditional stability and ease of design. A FIR filter is defined | 102 | 105 | We select FIR filters for their unconditional stability and ease of design. A FIR filter is defined | |
| by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the | 103 | 106 | by a set of weights $b_k$ applied to the inputs $x_k$ through a convolution to generate the | |
| outputs $y_k$ | 104 | 107 | outputs $y_k$ | |
| \begin{align} | 105 | 108 | \begin{align} | |
| y_n=\sum_{k=0}^N b_k x_{n-k} | 106 | 109 | y_n=\sum_{k=0}^N b_k x_{n-k} | |
| \label{eq:fir_equation} | 107 | 110 | \label{eq:fir_equation} | |
| \end{align} | 108 | 111 | \end{align} | |
| 109 | 112 | |||
| As opposed to an implementation on a general purpose processor in which word size is defined by the | 110 | 113 | As opposed to an implementation on a general purpose processor in which word size is defined by the | |
| processor architecture, implementing such a filter on an FPGA offer more degrees of freedom since | 111 | 114 | processor architecture, implementing such a filter on an FPGA offers more degrees of freedom since | |
| not only the coefficient values and number of taps must be defined, but also the number of bits | 112 | 115 | not only the coefficient values and number of taps must be defined, but also the number of bits | |
| defining the coefficients and the sample size. For this reason, and because we consider pipeline | 113 | 116 | defining the coefficients and the sample size. For this reason, and because we consider pipeline | |
| processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency | 114 | 117 | processing (as opposed to First-In, First-Out FIFO memory batch processing) of radiofrequency | |
| signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but | 115 | 118 | signals, High Level Synthesis (HLS) languages \cite{kasbah2008multigrid} are not considered but | |
| the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language (VHDL) level. | 116 | 119 | the problem is tackled at the Very-high-speed-integrated-circuit Hardware Description Language | |
| 120 | (VHDL) level. | |||
| Since latency is not an issue in a openloop phase noise characterization instrument, the large | 117 | 121 | Since latency is not an issue in a openloop phase noise characterization instrument, the large | |
| numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter, | 118 | 122 | numbre of taps in the FIR, as opposed to the shorter Infinite Impulse Response (IIR) filter, | |
| is not considered as an issue as would be in a closed loop system. | 119 | 123 | is not considered as an issue as would be in a closed loop system. | |
| 120 | 124 | |||
| The coefficients are classically expressed as floating point values. However, this binary | 121 | 125 | The coefficients are classically expressed as floating point values. However, this binary | |
| number representation is not efficient for fast arithmetic computation by an FPGA. Instead, | 122 | 126 | number representation is not efficient for fast arithmetic computation by an FPGA. Instead, | |
| we select to quantify these floating point values into integer values. This quantization | 123 | 127 | we select to quantify these floating point values into integer values. This quantization | |
| will result in some precision loss. | 124 | 128 | will result in some precision loss. | |
| 125 | 129 | |||
| \begin{figure}[h!tb] | 126 | 130 | \begin{figure}[h!tb] | |
| \includegraphics[width=\linewidth]{images/zero_values} | 127 | 131 | \includegraphics[width=\linewidth]{images/zero_values} | |
| \caption{Impact of the quantization resolution of the coefficients: the quantization is | 128 | 132 | \caption{Impact of the quantization resolution of the coefficients: the quantization is | |
| set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting | 129 | 133 | set to 6~bits -- with the horizontal black lines indicating $\pm$1 least significant bit -- setting | |
| the 30~first and 30~last coefficients out of the initial 128~band-pass | 130 | 134 | the 30~first and 30~last coefficients out of the initial 128~band-pass | |
| filter coefficients to 0 (red dots).} | 131 | 135 | filter coefficients to 0 (red dots).} | |
| \label{float_vs_int} | 132 | 136 | \label{float_vs_int} | |
| \end{figure} | 133 | 137 | \end{figure} | |
| 134 | 138 | |||
| The tradeoff between quantization resolution and number of coefficients when considering | 135 | 139 | The tradeoff between quantization resolution and number of coefficients when considering | |
| integer operations is not trivial. As an illustration of the issue related to the | 136 | 140 | integer operations is not trivial. As an illustration of the issue related to the | |
| relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits | 137 | 141 | relation between number of fiter taps and quantization, Fig. \ref{float_vs_int} exhibits | |
| a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon | 138 | 142 | a 128-coefficient FIR bandpass filter designed using floating point numbers (blue). Upon | |
| quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the | 139 | 143 | quantization on 6~bit integers, 60 of the 128~coefficients in the beginning and end of the | |
| taps become null, making the large number of coefficients irrelevant and allowing to save | 140 | 144 | taps become null, making the large number of coefficients irrelevant and allowing to save | |
| processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources | 141 | 145 | processing resource by shrinking the filter length. This tradeoff aimed at minimizing resources | |
| to reach a given rejection level, or maximizing out of band rejection for a given computational | 142 | 146 | to reach a given rejection level, or maximizing out of band rejection for a given computational | |
| resource, will drive the investigation on cascading filters designed with varying tap resolution | 143 | 147 | resource, will drive the investigation on cascading filters designed with varying tap resolution | |
| and tap length, as will be shown in the next section. Indeed, our development strategy closely | 144 | 148 | and tap length, as will be shown in the next section. Indeed, our development strategy closely | |
| follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards} | 145 | 149 | follows the skeleton approach \cite{crookes1998environment, crookes2000design, benkrid2002towards} | |
| in which basic blocks are defined and characterized before being assembled \cite{hide} | 146 | 150 | in which basic blocks are defined and characterized before being assembled \cite{hide} | |
| in a complete processing chain. In our case, assembling the filter blocks is a simpler block | 147 | 151 | in a complete processing chain. In our case, assembling the filter blocks is a simpler block | |
| combination process since we assume a single value to be processed and a single value to be | 148 | 152 | combination process since we assume a single value to be processed and a single value to be | |
| generated at each clock cycle. The FIR filters will not be considered to decimate in the | 149 | 153 | generated at each clock cycle. The FIR filters will not be considered to decimate in the | |
| current implementation: the decimation is assumed to be located after the FIR cascade at the | 150 | 154 | current implementation: the decimation is assumed to be located after the FIR cascade at the | |
| moment. | 151 | 155 | moment. | |
| 152 | 156 | |||
| \section{Methodology description} | 153 | 157 | \section{Methodology description} | |
| We want create a new methodology to develop any Digital Signal Processing (DSP) chain | 154 | |||
| and for any hardware platform (Altera, Xilinx...). To do this we have defined an | 155 | |||
| abstract model to represent some basic operations of DSP. | 156 | |||
| 157 | 158 | |||
| For the moment, we are focused on only two operations: the filtering and the shifting of data. | 158 | 159 | Our objective is to develop a new methodology applicable to any Digital Signal Processing (DSP) | |
| We have chosen this basic operation because the shifting and the filtering have already be studied in | 159 | 160 | chain obtained by assembling basic processing blocks, with hardware and manufacturer independence. | |
| lot of works \cite{lim_1996, lim_1988, young_1992, smith_1998} hence it will be easier | 160 | 161 | Achieving such a target requires defining an abstract model to represent some basic properties | |
| to check and validate our results. | 161 | 162 | of DSP blocks such as perfomance (i.e. rejection or ripples in the bandpass for filters) and | |
| 163 | resource occupation. These abstract properties, not necessarily related to the detailed hardware | |||
| 164 | implementation of a given platform, will feed a scheduler solver aimed at assembling the optimum | |||
| 165 | target, whether in terms of maximizing performance for a given arbitrary resource occupation, or | |||
| 166 | minimizing resource occupation for a given perfomance. In our approach, the solution of the | |||
| 167 | solver is then synthesized using the dedicated tool provided by each platform manufacturer | |||
| 168 | to assess the validity of our abstract resource occupation indicator, and the result of running | |||
| 169 | the DSP chain on the FPGA allows for assessing the performance of the scheduler. We emphasize | |||
| 170 | that all solutions found by the solver are synthesized and executed on hardware at the end | |||
| 171 | of the analysis. | |||
| 162 | 172 | |||
| However having only two operations is insufficient to work with complex DSP but | 163 | 173 | In this demonstration , we focus on only two operations: filtering and shifting the number of | |
| in this paper we only want demonstrate the relevance and the efficiency of our approach. | 164 | 174 | bits needed to represent the data along the processing chain. | |
| In future work it will be possible to add more operations and we are able to | 165 | 175 | We have chosen these basic operations because shifting and the filtering have already been studied | |
| model any DSP chain. | 166 | 176 | in the literature \cite{lim_1996, lim_1988, young_1992, smith_1998} providing a framework for | |
| 177 | assessing our results. Furthermore, filtering is a core step in any radiofrequency frontend | |||
| 178 | requiring pipelined processing at full bandwidth for the earliest steps, including for | |||
| 179 | time and frequency transfer or characterization \cite{carolina1,carolina2,rsi}. | |||
| 167 | 180 | |||
| We will apply our methodology on very simple DSP chain. We generate a digital signal | 168 | 181 | Addressing only two operations allows for demonstrating the methodology but should not be | |
| thanks at generator of Pseudo-Random Number (PRN) or thanks at an Analog to Digital | 169 | 182 | considered as a limitation of the framework which can be extended to assembling any number | |
| Converter (ADC). Once we have a digital signal, we filter it to decrease the noise level. | 170 | 183 | of skeleton blocks as long as perfomance and resource occupation can be determined. Hence, | |
| Finally we stored some burst of filtered samples before post-processing it. | 171 | 184 | in this paper we will apply our methodology on simple DSP chains: a white noise input signal | |
| In this particular case, we want optimize the filtering step to have the best noise | 172 | 185 | is generated using a Pseudo-Random Number (PRN) generator or thanks at a radiofrequency-grade | |
| rejection for constrain number of resource or to have the minimal resources | 173 | 186 | Analog to Digital Converter (ADC) loaded by a 50~$\Omega$ resistor. Once samples have been | |
| consumption for a given rejection objective. | 174 | 187 | digitized at a rate of 125~MS/s, filtering is applied to qualify the processing block performance -- | |
| 188 | practically meeting the radiofrequency frontend requirement of noise and bandwidth reduction | |||
| 189 | by filtering and decimating. Finally, bursts of filtered samples are stored for post-processing, | |||
| 190 | allowing to assess either filter rejection for a given resource usage, or validating the rejection | |||
| 191 | when implementing a solution minimizing resource occupation. | |||
| 175 | 192 | |||
| The first step of our approach is to model the DSP chain and since we just optimize | 176 | 193 | The first step of our approach is to model the DSP chain and since we just optimize | |
| the filtering, we have not modeling the PRN generator or the ADC. The filtering can be | 177 | 194 | the filtering, we have not modeling the PRN generator or the ADC. The filtering can be | |
| done by two ways. The first one we use only one FIR filter with lot of coefficients | 178 | 195 | done by two ways. The first one we use only one FIR filter with lot of coefficients | |
| to rejection the noise, we called this approach a monolithic approach. And the second one | 179 | 196 | to rejection the noise, we called this approach a monolithic approach. And the second one | |
| we select different FIR filters with less coefficients the monolithic filter and we cascaded | 180 | 197 | we select different FIR filters with less coefficients the monolithic filter and we cascaded | |
| it to filtering the signal. | 181 | 198 | it to filtering the signal. | |
| 182 | 199 | |||
| After each filter we leave the possibility of shifting the filtered data to consume | 183 | 200 | After each filter we leave the possibility of shifting the filtered data to consume | |
| less resources. Hence in the case of cascaded filter, we define a stage as a filter | 184 | 201 | less resources. Hence in the case of cascaded filter, we define a stage as a filter | |
| and a shifter (the shift could be omitted if we do not need to divide the filtered data). | 185 | 202 | and a shifter (the shift could be omitted if we do not need to divide the filtered data). | |
| 186 | 203 | |||
| \subsection{Model of a FIR filter} | 187 | 204 | \subsection{Model of a FIR filter} | |
| A cascade of filter are composed of $n$ stage. In stage $i$ ($1 \leq i \leq n$) | 188 | 205 | ||
| the FIR has $C_i$ coefficients and each coefficients are integer values with $\pi^C_i$ | 189 | 206 | A cascade of filters is composed of $n$ FIR stages. In stage $i$ ($1 \leq i \leq n$) | |
| bits and the filtered data are shifted of $\pi^S_i$ bits. We define also $\pi^-_i$ as | 190 | 207 | the FIR has $C_i$ coefficients and each coefficient is an integer value with $\pi^C_i$ | |
| 208 | bits while the filtered data are shifted by $\pi^S_i$ bits. We define also $\pi^-_i$ as | |||
| the size of input data and $\pi^+_i$ as the size of output data. The figure~\ref{fig:fir_stage} | 191 | 209 | the size of input data and $\pi^+_i$ as the size of output data. The figure~\ref{fig:fir_stage} | |
| shows a filtering stage. | 192 | 210 | shows a filtering stage. | |
| 193 | 211 | |||
| \begin{figure} | 194 | 212 | \begin{figure} | |
| \centering | 195 | 213 | \centering | |
| \begin{tikzpicture}[node distance=2cm] | 196 | 214 | \begin{tikzpicture}[node distance=2cm] | |
| \node[draw,minimum size=1.3cm] (FIR) { $C_i, \pi_i^C$ } ; | 197 | 215 | \node[draw,minimum size=1.3cm] (FIR) { $C_i, \pi_i^C$ } ; | |
| \node[draw,minimum size=1.3cm] (Shift) [right of=FIR, ] { $\pi_i^S$ } ; | 198 | 216 | \node[draw,minimum size=1.3cm] (Shift) [right of=FIR, ] { $\pi_i^S$ } ; | |
| \node (Start) [left of=FIR] { } ; | 199 | 217 | \node (Start) [left of=FIR] { } ; | |
| \node (End) [right of=Shift] { } ; | 200 | 218 | \node (End) [right of=Shift] { } ; | |
| 201 | 219 | |||
| \node[draw,fit=(FIR) (Shift)] (Filter) { } ; | 202 | 220 | \node[draw,fit=(FIR) (Shift)] (Filter) { } ; | |
| 203 | 221 | |||
| \draw[->] (Start) edge node [above] { $\pi_i^-$ } (FIR) ; | 204 | 222 | \draw[->] (Start) edge node [above] { $\pi_i^-$ } (FIR) ; | |
| \draw[->] (FIR) -- (Shift) ; | 205 | 223 | \draw[->] (FIR) -- (Shift) ; | |
| \draw[->] (Shift) edge node [above] { $\pi_i^+$ } (End) ; | 206 | 224 | \draw[->] (Shift) edge node [above] { $\pi_i^+$ } (End) ; | |
| \end{tikzpicture} | 207 | 225 | \end{tikzpicture} | |
| \caption{A single filter is composed of a FIR (on the left) and a Shifter (on the right)} | 208 | 226 | \caption{A single filter is composed of a FIR (on the left) and a Shifter (on the right)} | |
| \label{fig:fir_stage} | 209 | 227 | \label{fig:fir_stage} | |
| \end{figure} | 210 | 228 | \end{figure} | |
| 211 | 229 | |||
| FIR $i$ can reject $F(C_i, \pi_i^C)$ dB. $F$ is determined numerically. | 212 | 230 | FIR $i$ has been characterized through numerical simulation as able to reject $F(C_i, \pi_i^C)$ dB. | |
| To measure this rejection, we use GNU Octave software to design FIR filter coefficients thanks to two | 213 | 231 | This rejection has been computed using GNU Octave software FIR coefficient design functions | |
| algorithms (\texttt{firls} and \texttt{fir1}). | 214 | 232 | (\texttt{firls} and \texttt{fir1}). | |
| For each configuration $(C_i, \pi_i^C)$, we first create a FIR with floating point coefficients and a given $C_i$ number of coefficients. | 215 | 233 | For each configuration $(C_i, \pi_i^C)$, we first create a FIR with floating point coefficients and a given $C_i$ number of coefficients. | |
| Then, the floating point coefficients are discretized into integers. In order to ensure that the coefficients are coded on $\pi_i^C$~bits effectively, | 216 | 234 | Then, the floating point coefficients are discretized into integers. In order to ensure that the coefficients are coded on $\pi_i^C$~bits effectively, | |
| the coefficients are normalized by their absolute maximum before being scaled to integer coefficients. | 217 | 235 | the coefficients are normalized by their absolute maximum before being scaled to integer coefficients. | |
| At least one coefficient is coded on $\pi_i^C$~bits, and in practice only $b_{C_i/2}$ is coded on $\pi_i^C$~bits while the other are coded on very fewer bits. | 218 | 236 | At least one coefficient is coded on $\pi_i^C$~bits, and in practice only $b_{C_i/2}$ is coded on $\pi_i^C$~bits while the others are coded on much fewer bits. | |
| 219 | 237 | |||
| With these coefficients, the \texttt{freqz} function is used to estimate the magnitude of the filter. | 220 | 238 | With these coefficients, the \texttt{freqz} function is used to estimate the magnitude of the filter | |
| Comparing the performance between FIRs requires however a unique criterion. As shown in figure~\ref{fig:fir_mag}, | 221 | 239 | transfer function. | |
| the FIR magnitude exhibits two parts. | 222 | 240 | Comparing the performance between FIRs requires however defining a unique criterion. As shown in figure~\ref{fig:fir_mag}, | |
| 241 | the FIR magnitude exhibits two parts: we focus here on the transitions width and the rejection rather than on the | |||
| 242 | bandpass ripples as emphasized in \cite{lim_1988,lim_1996}. | |||
| 223 | 243 | |||
| \begin{figure} | 224 | 244 | \begin{figure} | |
| 245 | \begin{center} | |||
| 246 | \scalebox{0.8}{ | |||
| \centering | 225 | 247 | \centering | |
| \begin{tikzpicture}[scale=0.3] | 226 | 248 | \begin{tikzpicture}[scale=0.3] | |
| \draw[<->] (0,15) -- (0,0) -- (21,0) ; | 227 | 249 | \draw[<->] (0,15) -- (0,0) -- (21,0) ; | |
| \draw[thick] (0,12) -- (8,12) -- (20,0) ; | 228 | 250 | \draw[thick] (0,12) -- (8,12) -- (20,0) ; | |
| 229 | 251 | |||
| \draw (0,14) node [left] { $P$ } ; | 230 | 252 | \draw (0,14) node [left] { $P$ } ; | |
| \draw (20,0) node [below] { $f$ } ; | 231 | 253 | \draw (20,0) node [below] { $f$ } ; | |
| 232 | 254 | |||
| \draw[>=latex,<->] (0,14) -- (8,14) ; | 233 | 255 | \draw[>=latex,<->] (0,14) -- (8,14) ; | |
| \draw (4,14) node [above] { passband } node [below] { $40\%$ } ; | 234 | 256 | \draw (4,14) node [above] { passband } node [below] { $40\%$ } ; | |
| 235 | 257 | |||
| \draw[>=latex,<->] (8,14) -- (12,14) ; | 236 | 258 | \draw[>=latex,<->] (8,14) -- (12,14) ; | |
| \draw (10,14) node [above] { transition } node [below] { $20\%$ } ; | 237 | 259 | \draw (10,14) node [above] { transition } node [below] { $20\%$ } ; | |
| 238 | 260 | |||
| \draw[>=latex,<->] (12,14) -- (20,14) ; | 239 | 261 | \draw[>=latex,<->] (12,14) -- (20,14) ; | |
| \draw (16,14) node [above] { stopband } node [below] { $40\%$ } ; | 240 | 262 | \draw (16,14) node [above] { stopband } node [below] { $40\%$ } ; | |
| 241 | 263 | |||
| \draw[>=latex,<->] (16,12) -- (16,8) ; | 242 | 264 | \draw[>=latex,<->] (16,12) -- (16,8) ; | |
| \draw (16,10) node [right] { rejection } ; | 243 | 265 | \draw (16,10) node [right] { rejection } ; | |
| 244 | 266 | |||
| \draw[dashed] (8,-1) -- (8,14) ; | 245 | 267 | \draw[dashed] (8,-1) -- (8,14) ; | |
| \draw[dashed] (12,-1) -- (12,14) ; | 246 | 268 | \draw[dashed] (12,-1) -- (12,14) ; | |
| 247 | 269 | |||
| \draw[dashed] (8,12) -- (16,12) ; | 248 | 270 | \draw[dashed] (8,12) -- (16,12) ; | |
| \draw[dashed] (12,8) -- (16,8) ; | 249 | 271 | \draw[dashed] (12,8) -- (16,8) ; | |
| 250 | 272 | |||
| \end{tikzpicture} | 251 | 273 | \end{tikzpicture} | |
| 274 | } | |||
| 275 | \end{center} | |||
| \caption{Shape of the filter transmitted power $P$ as a function of frequency $f$: | 252 | 276 | \caption{Shape of the filter transmitted power $P$ as a function of frequency $f$: | |
| the passband is considered to occupy the initial 40\% of the Nyquist frequency range, | 253 | 277 | the passband is considered to occupy the initial 40\% of the Nyquist frequency range, | |
| the stopband the last 40\%, allowing 20\% transition width.} | 254 | 278 | the stopband the last 40\%, allowing 20\% transition width.} | |
| \label{fig:fir_mag} | 255 | 279 | \label{fig:fir_mag} | |
| \end{figure} | 256 | 280 | \end{figure} | |
| 257 | 281 | |||
| In the transition band, the behavior of the filter is left free, we only care about the passband and the stopband. | 258 | 282 | In the transition band, the behavior of the filter is left free, we only care about the passband and the stopband characteristics. | |
| Our first criterion considers the mean value of the stopband rejection, as shown in figure~\ref{fig:mean_criterion}. This criterion does not work because we do not consider the shape of the passband. | 259 | 283 | Our initial criterion considered the mean value of the stopband rejection, as shown in figure~\ref{fig:mean_criterion}. This criterion | |
| A second criterion considers the maximum rejection within the stopband minus the mean of the absolute value of passband rejection. With this criterion, the results are significantly improved as shown in figure~\ref{fig:custom_criterion}. | 260 | 284 | yields unacceptable results since notches overestimate the rejection capability of the filter. Furthermore, the losses within | |
| 285 | the passband are not considered and might be excessive for excessively wide transitions widths introduced for filters with few coefficients. | |||
| 286 | Such biases are compensated for by the second considered criterion which is based on computing the maximum rejection within the stopband minus the mean of the absolute value of passband rejection. With this criterion, the results are significantly improved as shown in figure~\ref{fig:custom_criterion} and meet the expected rejection capability of low pass filters. | |||
| 261 | 287 | |||
| \begin{figure} | 262 | 288 | \begin{figure} | |
| \centering | 263 | 289 | \centering | |
| \includegraphics[width=\linewidth]{images/colored_mean_criterion} | 264 | 290 | \includegraphics[width=\linewidth]{images/colored_mean_criterion} | |
| \caption{Mean criterion comparison between monolithic filter and cascade filters} | 265 | 291 | \caption{Mean stopband rejection criterion comparison between monolithic filter and cascaded filters} | |
| \label{fig:mean_criterion} | 266 | 292 | \label{fig:mean_criterion} | |
| \end{figure} | 267 | 293 | \end{figure} | |
| 268 | 294 | |||
| \begin{figure} | 269 | 295 | \begin{figure} | |
| \centering | 270 | 296 | \centering | |
| \includegraphics[width=\linewidth]{images/colored_custom_criterion} | 271 | 297 | \includegraphics[width=\linewidth]{images/colored_custom_criterion} | |
| \caption{Custom criterion comparison between monolithic filter and cascade filters} | 272 | 298 | \caption{Custom criterion (maximum rejection in the stopband minus the mean of the absolute value of the passband rejection) | |
| 299 | comparison between monolithic filter and cascaded filters} | |||
| \label{fig:custom_criterion} | 273 | 300 | \label{fig:custom_criterion} | |
| \end{figure} | 274 | 301 | \end{figure} | |
| 275 | 302 | |||
| Thanks to this criterion we are able to automatically generate lot of fir coefficients | 276 | 303 | Thanks to the latter criterion which will be used in the remainder of this paper, we are able to automatically generate multiple FIR taps | |
| and estimate their rejection. The figure~\ref{fig:rejection_pyramid} exhibits the | 277 | 304 | and estimate their rejection. Figure~\ref{fig:rejection_pyramid} exhibits the | |
| rejection in function of the number of coefficients and their number of bits. | 278 | 305 | rejection as a function of the number of coefficients and the number of bits representing these coefficients. | |
| We can observe it looks like a pyramid so the edge represents the best | 279 | 306 | The curve shaped as a pyramid exhibits optimum configurations sets at the vertex where both edges meet. | |
| coefficient set. Indeed if we choose a number of coefficients, increasing the number | 280 | 307 | Indeed for a given number of coefficients, increasing the number of bits over the edge will not improve the rejection. | |
| of bits over the edge will not improve the rejection. Conversely when we choose | 281 | 308 | Conversely when setting the a given number of bits, increasing the number of coefficients will not improve | |
| a number of bits, too much increase the number of coefficients will not improve | 282 | 309 | the rejection. Hence the best coefficient set are on the vertex of the pyramid. | |
| the rejection. Hence the best coefficient set are on the edge of pyramid. | 283 | |||
| 284 | 310 | |||
| \begin{figure} | 285 | 311 | \begin{figure} | |
| \centering | 286 | 312 | \centering | |
| \includegraphics[width=\linewidth]{images/rejection_pyramid} | 287 | 313 | \includegraphics[width=\linewidth]{images/rejection_pyramid} | |
| \caption{Rejection as a function of number of coefficients and number of bits} | 288 | 314 | \caption{Rejection as a function of number of coefficients and number of bits} | |
| \label{fig:rejection_pyramid} | 289 | 315 | \label{fig:rejection_pyramid} | |
| \end{figure} | 290 | 316 | \end{figure} | |
| 291 | 317 | |||
| Although we have a efficient criterion to estimate the rejection of one set of coefficient | 292 | 318 | Although we have an efficient criterion to estimate the rejection of one set of coefficients (taps), | |
| we have a problem when we sum two or more criterion. If the FIR filter coefficients are the same | 293 | 319 | we have a problem when we cascade filters and estimate the criterion as a sum two or more individual criteria. | |
| between the stage, we have: | 294 | 320 | If the FIR filter coefficients are the same between the stages, we have: | |
| $$F_{total} = F_1 + F_2$$ | 295 | 321 | $$F_{total} = F_1 + F_2$$ | |
| But when we choose two different set of coefficient, the previous equality are not | 296 | 322 | But selecting two different sets of coefficient will yield a more complex situation in which | |
| true. The figure~\ref{fig:sum_rejection} illustrates the problem. The red and blue curves | 297 | 323 | the previous relation is no longer valid as illustrated on figure~\ref{fig:sum_rejection}. The red and blue curves | |
| are two different filter coefficient and we can see that their maximum on the stopband | 298 | 324 | are two different filters with maximums and notches not located at the same frequency offsets. | |
| are not at the same frequency. So when we sum the rejection criteria (the dotted yellow line) | 299 | 325 | Hence when summing the transfer functions, the resulting rejection shown as the dashed yellow line is improved | |
| we do not meet the dashed yellow line. Define the rejection of cascaded filters | 300 | 326 | with respect to a basic sum of the rejection criteria shown as a the dotted yellow line. | |
| is more difficult than just take the summation between all the rejection criteria of each filter. | 301 | 327 | Thus, estimating the rejection of filter cascades is more complex than takin the sum of all the rejection | |
| However this summation gives us an upper bound for rejection although in fact we obtain | 302 | 328 | criteria of each filter. However since the this sum underestimates the rejection capability of the cascade, | |
| better rejection than expected. | 303 | 329 | this upper bound is considered as a pessimistic and acceptable criterion for deciding on the suitability | |
| 330 | of the filter cascade to meet design criteria. | |||
| 304 | 331 | |||
| \begin{figure} | 305 | 332 | \begin{figure} | |
| \centering | 306 | 333 | \centering | |
| \includegraphics[width=\linewidth]{images/cascaded_criterion} | 307 | 334 | \includegraphics[width=\linewidth]{images/cascaded_criterion} | |
| \caption{Rejection of two cascaded filters} | 308 | 335 | \caption{Rejection of two cascaded filters} | |
| \label{fig:sum_rejection} | 309 | 336 | \label{fig:sum_rejection} | |
| \end{figure} | 310 | 337 | \end{figure} | |
| 311 | 338 | |||
| The first problem we address is to maximize the rejection under bounded silicon area | 312 | 339 | Based on this analysis, we address the estimate of resource consumption (called | |
| and feasibility constraints. Variable $a_i$ is the area taken by filter~$i$ | 313 | 340 | silicon area -- in the case of FPGAs meaning processing cells) as a function of | |
| 341 | filter characteristics. As a reminder, we do not aim at matching actual hardware | |||
| 342 | configuration but consider an arbitrary silicon area occupied by each processing function, | |||
| 343 | and will assess after synthesis the adequation of this arbitrary unit with actual | |||
| 344 | hardware resources provided by FPGA manufacturers. The sum of individual processing | |||
| 345 | unit areas is constrained by a total silicon area representative of FPGA global resources. | |||
| 346 | Formally, variable $a_i$ is the area taken by filter~$i$ | |||
| (in arbitrary unit). Variable $r_i$ is the rejection of filter~$i$ (in dB). | 314 | 347 | (in arbitrary unit). Variable $r_i$ is the rejection of filter~$i$ (in dB). | |
| Constant $\mathcal{A}$ is the total available area. We model our problem as follows: | 315 | 348 | Constant $\mathcal{A}$ is the total available area. We model our problem as follows: | |
| 316 | 349 | |||
| Finally we can describe our abstract model with following expressions : | 317 | |||
| \begin{align} | 318 | 350 | \begin{align} | |
| \text{Maximize } & \sum_{i=1}^n r_i \notag \\ | 319 | 351 | \text{Maximize } & \sum_{i=1}^n r_i \notag \\ | |
| \sum_{i=1}^n a_i & \leq \mathcal{A} & \label{eq:area} \\ | 320 | 352 | \sum_{i=1}^n a_i & \leq \mathcal{A} & \label{eq:area} \\ | |
| a_i & = C_i \times (\pi_i^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef} \\ | 321 | 353 | a_i & = C_i \times (\pi_i^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef} \\ | |
| r_i & = F(C_i, \pi_i^C), & \forall i \in [1, n] \label{eq:rejectiondef} \\ | 322 | 354 | r_i & = F(C_i, \pi_i^C), & \forall i \in [1, n] \label{eq:rejectiondef} \\ | |
| \pi_i^+ & = \pi_i^- + \pi_i^C - \pi_i^S, & \forall i \in [1, n] \label{eq:bits} \\ | 323 | 355 | \pi_i^+ & = \pi_i^- + \pi_i^C - \pi_i^S, & \forall i \in [1, n] \label{eq:bits} \\ | |
| \pi_{i - 1}^+ & = \pi_i^-, & \forall i \in [2, n] \label{eq:inout} \\ | 324 | 356 | \pi_{i - 1}^+ & = \pi_i^-, & \forall i \in [2, n] \label{eq:inout} \\ | |
| \pi_i^+ & \geq 1 + \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right), & \forall i \in [1, n] \label{eq:maxshift} \\ | 325 | 357 | \pi_i^+ & \geq 1 + \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right), & \forall i \in [1, n] \label{eq:maxshift} \\ | |
| \pi_1^- &= \Pi^I \label{eq:init} | 326 | 358 | \pi_1^- &= \Pi^I \label{eq:init} | |
| \end{align} | 327 | 359 | \end{align} | |
| 328 | 360 | |||
| Equation~\ref{eq:area} states that the total area taken by the filters must be | 329 | 361 | Equation~\ref{eq:area} states that the total area taken by the filters must be | |
| less than the available area. Equation~\ref{eq:areadef} gives the definition of | 330 | 362 | less than the available area. Equation~\ref{eq:areadef} gives the definition of | |
| the area for a filter. More precisely, it is the area of the FIR as the Shifter | 331 | 363 | the area used by a filter, considered as the area of the FIR since the Shifter is | |
| does not need any circuitry. We consider that the FIR needs $C_i$ registers of size | 332 | 364 | assumed not to require significant resources. We consider that the FIR needs $C_i$ registers of size | |
| $\pi_i^C + \pi_i^-$~bits to store the results of the multiplications of the | 333 | 365 | $\pi_i^C + \pi_i^-$~bits to store the results of the multiplications of the | |
| input data and the coefficients. Equation~\ref{eq:rejectiondef} gives the | 334 | 366 | input data with the coefficients. Equation~\ref{eq:rejectiondef} gives the | |
| definition of the rejection of the filter thanks to function~$F$ that we defined | 335 | 367 | definition of the rejection of the filter thanks to the tabulated function~$F$ that we defined | |
| previously. The Shifter does not introduce negative rejection as we explain later, | 336 | 368 | previously. The Shifter does not introduce negative rejection as we will explain later, | |
| so the rejection only comes from the FIR. Equation~\ref{eq:bits} states the | 337 | 369 | so the rejection only comes from the FIR. Equation~\ref{eq:bits} states the | |
| relation between $\pi_i^+$ and $\pi_i^-$. The multiplications in the FIR add | 338 | 370 | relation between $\pi_i^+$ and $\pi_i^-$. The multiplications in the FIR add | |
| $\pi_i^C$ bits as most coefficients are close to zero, and the Shifter removes | 339 | 371 | $\pi_i^C$ bits as most coefficients are close to zero, and the Shifter removes | |
| $\pi_i^S$ bits. Equation~\ref{eq:inout} states that the output number of bits of | 340 | 372 | $\pi_i^S$ bits. Equation~\ref{eq:inout} states that the output number of bits of | |
| a filter is the same as the input number of bits of the next filter. | 341 | 373 | a filter is the same as the input number of bits of the next filter. | |
| Equation~\ref{eq:maxshift} ensures that the Shifter does not introduce negative | 342 | 374 | Equation~\ref{eq:maxshift} ensures that the Shifter does not introduce negative | |
| rejection. Indeed, the results of the FIR can be right shifted without compromising | 343 | 375 | rejection. Indeed, the results of the FIR can be right shifted without compromising | |
| the quality of the rejection until a threshold. Each bit of the output data | 344 | 376 | the quality of the rejection until a threshold. Each bit of the output data | |
| increases the maximum rejection level of 6~dB. We add one to take the sign bit | 345 | 377 | increases the maximum rejection level by 6~dB. We add one to take the sign bit | |
| into account. If equation~\ref{eq:maxshift} was not present, the Shifter could | 346 | 378 | into account. If equation~\ref{eq:maxshift} was not present, the Shifter could | |
| shift too much and introduce some noise in the output data. Each supplementary | 347 | 379 | shift too much and introduce some noise in the output data. Each supplementary | |
| shift bit would cause 6~dB of noise. A totally equivalent equation is: | 348 | 380 | shift bit would cause an additional 6~dB rejection rise. A totally equivalent equation is: | |
| $\pi_i^S \leq \pi_i^- + \pi_i^C - 1 - \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right) $. | 349 | 381 | $\pi_i^S \leq \pi_i^- + \pi_i^C - 1 - \sum_{k=1}^{i} \left(1 + \frac{r_j}{6}\right)$. | |
| Finally, equation~\ref{eq:init} gives the global input's number of bits. | 350 | 382 | Finally, equation~\ref{eq:init} gives the number of bits of the global input. | |
| 351 | 383 | |||
| This model is non-linear and even non-quadratic, as $F$ does not have a known | 352 | 384 | This model is non-linear and even non-quadratic, as $F$ does not have a known | |
| linear or quadratic expression. We introduce $p$ FIR configurations | 353 | 385 | linear or quadratic expression. We introduce $p$ FIR configurations | |
| $(C_{ij}, \pi_{ij}^C), 1 \leq j \leq p$ that are constants. We define binary | 354 | 386 | $(C_{ij}, \pi_{ij}^C), 1 \leq j \leq p$ that are constants. We define binary | |
| variable $\delta_{ij}$ that has value 1 if stage~$i$ is in configuration~$j$ | 355 | 387 | variable $\delta_{ij}$ that has value 1 if stage~$i$ is in configuration~$j$ | |
| and 0 otherwise. The new equations are as follows: | 356 | 388 | and 0 otherwise. The new equations are as follows: | |
| 357 | 389 | |||
| \begin{align} | 358 | 390 | \begin{align} | |
| a_i & = \sum_{j=1}^p \delta_{ij} \times C_{ij} \times (\pi_{ij}^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef2} \\ | 359 | 391 | a_i & = \sum_{j=1}^p \delta_{ij} \times C_{ij} \times (\pi_{ij}^C + \pi_i^-), & \forall i \in [1, n] \label{eq:areadef2} \\ | |
| r_i & = \sum_{j=1}^p \delta_{ij} \times F(C_{ij}, \pi_{ij}^C), & \forall i \in [1, n] \label{eq:rejectiondef2} \\ | 360 | 392 | r_i & = \sum_{j=1}^p \delta_{ij} \times F(C_{ij}, \pi_{ij}^C), & \forall i \in [1, n] \label{eq:rejectiondef2} \\ | |
| \pi_i^+ & = \pi_i^- + \left(\sum_{j=1}^p \delta_{ij} \pi_{ij}^C\right) - \pi_i^S, & \forall i \in [1, n] \label{eq:bits2} \\ | 361 | 393 | \pi_i^+ & = \pi_i^- + \left(\sum_{j=1}^p \delta_{ij} \pi_{ij}^C\right) - \pi_i^S, & \forall i \in [1, n] \label{eq:bits2} \\ | |
| \sum_{j=1}^p \delta_{ij} & \leq 1, & \forall i \in [1, n] \label{eq:config} | 362 | 394 | \sum_{j=1}^p \delta_{ij} & \leq 1, & \forall i \in [1, n] \label{eq:config} | |
| \end{align} | 363 | 395 | \end{align} | |
| 364 | 396 | |||
| Equations \ref{eq:areadef2}, \ref{eq:rejectiondef2} and \ref{eq:bits2} replace | 365 | 397 | Equations \ref{eq:areadef2}, \ref{eq:rejectiondef2} and \ref{eq:bits2} replace | |
| respectively equations \ref{eq:areadef}, \ref{eq:rejectiondef} and \ref{eq:bits}. | 366 | 398 | respectively equations \ref{eq:areadef}, \ref{eq:rejectiondef} and \ref{eq:bits}. | |
| Equation~\ref{eq:config} states that for each stage, a single configuration is chosen at most. | 367 | 399 | Equation~\ref{eq:config} states that for each stage, a single configuration is chosen at most. | |
| 368 | 400 | |||
| This modified model is quadratic, and it can be linearised if necessary. The Gurobi | 369 | 401 | This modified model is quadratic, and it can be linearised if necessary. The Gurobi | |
| (\url{www.gurobi.com}) optimization software is used to solve this quadratic | 370 | 402 | (\url{www.gurobi.com}) optimization software is used to solve this quadratic | |
| model, and since Gurobi is able to linearize, the model is left as is. This model | 371 | 403 | model, and since Gurobi is able to linearize, the model is left as is. This model | |
| has $O(np)$ variables and $O(n)$ constraints. | 372 | 404 | has $O(np)$ variables and $O(n)$ constraints. | |
| 373 | 405 | |||
| The section~\ref{sec:fixed_area} shows the results for the first version of quadratic program but the section~\ref{sec:fixed_rej} | 374 | 406 | Two problems will be addressed using the workflow described in the next section: on the one | |
| presents the results for the complementary problem. In this case we want | 375 | 407 | hand maximizing the rejection capability of a set of cascaded filters occupying a fixed arbitrary | |
| minimize the occupied area for a targeted rejection level. Hence we have replace | 376 | 408 | silcon area (section~\ref{sec:fixed_area}) and on the second hand the dual problem of minimizing the silicon area | |
| the objective function with: | 377 | 409 | for a fixed rejection criterion (section~\ref{sec:fixed_rej}). In the latter case, the | |
| 410 | objective function is replaced with: | |||
| \begin{align} | 378 | 411 | \begin{align} | |
| \text{Minimize } & \sum_{i=1}^n a_i \notag | 379 | 412 | \text{Minimize } & \sum_{i=1}^n a_i \notag | |
| \end{align} | 380 | 413 | \end{align} | |
| We adapt our constraints of quadratic program to replace the equation \ref{eq:area} | 381 | 414 | We adapt our constraints of quadratic program to replace equation \ref{eq:area} | |
| by the equation \ref{eq:rejection_min} where $\mathcal{R}$ is the minimal | 382 | 415 | with equation \ref{eq:rejection_min} where $\mathcal{R}$ is the minimal | |
| rejection required. | 383 | 416 | rejection required. | |
| 384 | 417 | |||
| \begin{align} | 385 | 418 | \begin{align} | |
| \sum_{i=1}^n r_i & \geq \mathcal{R} & \label{eq:rejection_min} | 386 | 419 | \sum_{i=1}^n r_i & \geq \mathcal{R} & \label{eq:rejection_min} | |
| \end{align} | 387 | 420 | \end{align} | |
| 388 | 421 | |||
| \section{Design workflow} | 389 | 422 | \section{Design workflow} | |
| \label{sec:workflow} | 390 | 423 | \label{sec:workflow} | |
| 391 | 424 | |||
| In this section, we describe the workflow to compute all the results presented in section~\ref{sec:fixed_area}. | 392 | 425 | In this section, we describe the workflow to compute all the results presented in sections~\ref{sec:fixed_area} | |
| Figure~\ref{fig:workflow} shows the global workflow and the different steps involved in the computations of the results. | 393 | 426 | and \ref{sec:fixed_rej}. Figure~\ref{fig:workflow} shows the global workflow and the different steps involved | |
| 427 | in the computation of the results. | |||
| 394 | 428 | |||
| \begin{figure} | 395 | 429 | \begin{figure} | |
| \centering | 396 | 430 | \centering | |
| \begin{tikzpicture}[node distance=0.75cm and 2cm] | 397 | 431 | \begin{tikzpicture}[node distance=0.75cm and 2cm] | |
| \node[draw,minimum size=1cm] (Solver) { Filter Solver } ; | 398 | 432 | \node[draw,minimum size=1cm] (Solver) { Filter Solver } ; | |
| \node (Start) [left= 3cm of Solver] { } ; | 399 | 433 | \node (Start) [left= 3cm of Solver] { } ; | |
| \node[draw,minimum size=1cm] (TCL) [right= of Solver] { TCL Script } ; | 400 | 434 | \node[draw,minimum size=1cm] (TCL) [right= of Solver] { TCL Script } ; | |
| \node (Input) [above= of TCL] { } ; | 401 | 435 | \node (Input) [above= of TCL] { } ; | |
| \node[draw,minimum size=1cm] (Deploy) [below= of Solver] { Deploy Script } ; | 402 | 436 | \node[draw,minimum size=1cm] (Deploy) [below= of Solver] { Deploy Script } ; | |
| \node[draw,minimum size=1cm] (Bitstream) [below= of TCL] { Bitstream } ; | 403 | 437 | \node[draw,minimum size=1cm] (Bitstream) [below= of TCL] { Bitstream } ; | |
| \node[draw,minimum size=1cm,rounded corners] (Board) [below right= of Deploy] { Board } ; | 404 | 438 | \node[draw,minimum size=1cm,rounded corners] (Board) [below right= of Deploy] { Board } ; | |
| \node[draw,minimum size=1cm] (Postproc) [below= of Deploy] { Post-Processing } ; | 405 | 439 | \node[draw,minimum size=1cm] (Postproc) [below= of Deploy] { Post-Processing } ; | |
| \node (Results) [left= of Postproc] { } ; | 406 | 440 | \node (Results) [left= of Postproc] { } ; | |
| 407 | 441 | |||
| \draw[->] (Start) edge node [above] { $\mathcal{A}, n, \Pi^I$ } node [below] { $(C_{ij}, \pi_{ij}^C), F$ } (Solver) ; | 408 | 442 | \draw[->] (Start) edge node [above] { $\mathcal{A}, n, \Pi^I$ } node [below] { $(C_{ij}, \pi_{ij}^C), F$ } (Solver) ; | |
| \draw[->] (Input) edge node [left] { ADC or PRN } (TCL) ; | 409 | 443 | \draw[->] (Input) edge node [left] { ADC or PRN } (TCL) ; | |
| \draw[->] (Solver) edge node [below] { (1a) } (TCL) ; | 410 | 444 | \draw[->] (Solver) edge node [below] { (1a) } (TCL) ; | |
| \draw[->] (Solver) edge node [right] { (1b) } (Deploy) ; | 411 | 445 | \draw[->] (Solver) edge node [right] { (1b) } (Deploy) ; | |
| \draw[->] (TCL) edge node [left] { (2) } (Bitstream) ; | 412 | 446 | \draw[->] (TCL) edge node [left] { (2) } (Bitstream) ; | |
| \draw[->,dashed] (Bitstream) -- (Deploy) ; | 413 | 447 | \draw[->,dashed] (Bitstream) -- (Deploy) ; | |
| \draw[->] (Deploy) to[out=-30,in=120] node [above] { (3) } (Board) ; | 414 | 448 | \draw[->] (Deploy) to[out=-30,in=120] node [above] { (3) } (Board) ; | |
| \draw[->] (Board) to[out=150,in=-60] node [below] { (4) } (Deploy) ; | 415 | 449 | \draw[->] (Board) to[out=150,in=-60] node [below] { (4) } (Deploy) ; | |
| \draw[->] (Deploy) edge node [left] { (5) } (Postproc) ; | 416 | 450 | \draw[->] (Deploy) edge node [left] { (5) } (Postproc) ; | |
| \draw[->] (Postproc) -- (Results) ; | 417 | 451 | \draw[->] (Postproc) -- (Results) ; | |
| \end{tikzpicture} | 418 | 452 | \end{tikzpicture} | |
| \caption{Design workflow from the input parameters to the results} | 419 | 453 | \caption{Design workflow from the input parameters to the results} | |
| \label{fig:workflow} | 420 | 454 | \label{fig:workflow} | |
| \end{figure} | 421 | 455 | \end{figure} | |
| 422 | 456 | |||
| The filter solver is a C++ program that takes as input the maximum area | 423 | 457 | The filter solver is a C++ program that takes as input the maximum area | |
| $\mathcal{A}$, the number of stages $n$, the size of the input signal $\Pi^I$, | 424 | 458 | $\mathcal{A}$, the number of stages $n$, the size of the input signal $\Pi^I$, | |
| the FIR configurations $(C_{ij}, \pi_{ij}^C)$ and the function $F$. It creates | 425 | 459 | the FIR configurations $(C_{ij}, \pi_{ij}^C)$ and the function $F$. It creates | |
| the quadratic programs and uses the Gurobi solver to get the optimal results. | 426 | 460 | the quadratic programs and uses the Gurobi solver to estimate the optimal results. | |
| Then it produces two scripts: a TCL script ((1a) on figure~\ref{fig:workflow}) | 427 | 461 | Then it produces two scripts: a TCL script ((1a) on figure~\ref{fig:workflow}) | |
| and a deploy script ((1b) on figure~\ref{fig:workflow}). | 428 | 462 | and a deploy script ((1b) on figure~\ref{fig:workflow}). | |
| 429 | 463 | |||
| The TCL script describes the whole digital processing chain from the beginning | 430 | 464 | The TCL script describes the whole digital processing chain from the beginning | |
| (the raw signal data) to the end (the filtered data). | 431 | 465 | (the raw signal data) to the end (the filtered data) in a language compatible | |
| The raw input data generated from a Pseudo Random Number (PRN) | 432 | 466 | with proprietary synthesis software, namely Vivado for Xilinx and Quartus for | |
| 467 | Intel/Altera. The raw input data generated from a 20-bit Pseudo Random Number (PRN) | |||
| generator inside the FPGA and $\Pi^I$ is fixed at 16~bits. | 433 | 468 | generator inside the FPGA and $\Pi^I$ is fixed at 16~bits. | |
| Then the script builds each stage of the chain with a generic FIR task that | 434 | 469 | Then the script builds each stage of the chain with a generic FIR task that | |
| comes from a skeleton library. The generic FIR is highly configurable | 435 | 470 | comes from a skeleton library. The generic FIR is highly configurable | |
| with the number of coefficients and the size of the coefficients. The coefficients | 436 | 471 | with the number of coefficients and the size of the coefficients. The coefficients | |
| themselves are not stored in the script. | 437 | 472 | themselves are not stored in the script. | |
| Whereas the signal is processed in real-time, the output signal is stored as | 438 | 473 | As the signal is processed in real-time, the output signal is stored as | |
| consecutive bursts of data. | 439 | 474 | consecutive bursts of data for post-processing, mainly assessing the consistency of the | |
| 475 | implemented FIR cascade transfer function with the design criteria and the expected | |||
| 476 | transfer function. | |||
| 440 | 477 | |||
| The TCL script is used by Vivado to produce the FPGA bitstream ((2) on figure~\ref{fig:workflow}). | 441 | 478 | The TCL script is used by Vivado to produce the FPGA bitstream ((2) on figure~\ref{fig:workflow}). | |
| We use the 2018.2 version of Xilinx Vivado and we execute the synthesized | 442 | 479 | We use the 2018.2 version of Xilinx Vivado and we execute the synthesized | |
| bitstream on a Redpitaya board fitted with a Xilinx Zynq-7010 series | 443 | 480 | bitstream on a Redpitaya board fitted with a Xilinx Zynq-7010 series | |
| FPGA (xc7z010clg400-1) and two 125~MS/s ADC. | 444 | 481 | FPGA (xc7z010clg400-1) and two LTC2145 14-bit 125~MS/s ADC, loaded with 50~$\Omega$ resistors to | |
| The board works with a Buildroot Linux image. We have developed some tools and | 445 | 482 | provide a broadband noise source. | |
| drivers to flash and communicate with the FPGA. They are used to automatize all | 446 | 483 | The board runs the Linux kernel and surrounding environment produced from the | |
| the workflow inside the board: load the filter coefficients and retrieve the | 447 | 484 | Buildroot framework available at \url{https://github.com/trabucayre/redpitaya/}: configuring | |
| computed data. | 448 | 485 | the Zynq FPGA, feeding the FIR with the set of coefficients, executing the simulation and | |
| 486 | fetching the results is automated. | |||
| 449 | 487 | |||
| The deploy script uploads the bitstream to the board ((3) on | 450 | 488 | The deploy script uploads the bitstream to the board ((3) on | |
| figure~\ref{fig:workflow}), flashes the FPGA, loads the different drivers, | 451 | 489 | figure~\ref{fig:workflow}), flashes the FPGA, loads the different drivers, | |
| configures the coefficients of the FIR filters. It then waits for the results | 452 | 490 | configures the coefficients of the FIR filters. It then waits for the results | |
| and retrieves the data to the main computer ((4) on figure~\ref{fig:workflow}). | 453 | 491 | and retrieves the data to the main computer ((4) on figure~\ref{fig:workflow}). | |
| 454 | 492 | |||
| Finally, an Octave post-processing script computes the final results thanks to | 455 | 493 | Finally, an Octave post-processing script computes the final results thanks to | |
| the output data ((5) on figure~\ref{fig:workflow}). | 456 | 494 | the output data ((5) on figure~\ref{fig:workflow}). | |
| The results are normalized so that the Power Spectrum Density (PSD) starts at zero | 457 | 495 | The results are normalized so that the Power Spectrum Density (PSD) starts at zero | |
| and the different configurations can be compared. | 458 | 496 | and the different configurations can be compared. | |
| 459 | 497 | |||
| The workflow used to compute the results in section~\ref{sec:fixed_rej}, we | 460 | 498 | \section{Maximizing the rejection at fixed silicon area} | |
| have just adapted the quadratic program but the rest of the workflow is unchanged. | 461 | |||
| 462 | ||||
| \section{Experiments with fixed area space} | 463 | |||
| \label{sec:fixed_area} | 464 | 499 | \label{sec:fixed_area} | |
| This section presents the output of the filter solver {\em i.e.} the computed | 465 | 500 | This section presents the output of the filter solver {\em i.e.} the computed | |
| configurations for each stage, the computed rejection and the computed silicon area. | 466 | 501 | configurations for each stage, the computed rejection and the computed silicon area. | |
| This is interesting to understand the choices made by the solver to compute its solutions. | 467 | 502 | Such results allow for understanding the choices made by the solver to compute its solutions. | |
| 468 | 503 | |||
| The experimental setup is composed of three cases. The raw input is generated | 469 | 504 | The experimental setup is composed of three cases. The raw input is generated | |
| by a Pseudo Random Number (PRN) generator, which fixes the input data size $\Pi^I$. | 470 | 505 | by a Pseudo Random Number (PRN) generator, which fixes the input data size $\Pi^I$. | |
| Then the total silicon area $\mathcal{A}$ has been fixed to either 500, 1000 or 1500 | 471 | 506 | Then the total silicon area $\mathcal{A}$ has been fixed to either 500, 1000 or 1500 | |
| arbitrary units. Hence, the three cases have been named: MAX/500, MAX/1000, MAX/1500. | 472 | 507 | arbitrary units. Hence, the three cases have been named: MAX/500, MAX/1000, MAX/1500. | |
| The number of configurations $p$ is 1827, with $C_i$ ranging from 3 to 60 and $\pi^C$ | 473 | 508 | The number of configurations $p$ is 1827, with $C_i$ ranging from 3 to 60 and $\pi^C$ | |
| ranging from 2 to 22. In each case, the quadratic program has been able to give a | 474 | 509 | ranging from 2 to 22. In each case, the quadratic program has been able to give a | |
| result up to five stages ($n = 5$) in the cascaded filter. | 475 | 510 | result up to five stages ($n = 5$) in the cascaded filter. | |
| 476 | 511 | |||
| Table~\ref{tbl:gurobi_max_500} shows the results obtained by the filter solver for MAX/500. | 477 | 512 | Table~\ref{tbl:gurobi_max_500} shows the results obtained by the filter solver for MAX/500. | |
| Table~\ref{tbl:gurobi_max_1000} shows the results obtained by the filter solver for MAX/1000. | 478 | 513 | Table~\ref{tbl:gurobi_max_1000} shows the results obtained by the filter solver for MAX/1000. | |
| Table~\ref{tbl:gurobi_max_1500} shows the results obtained by the filter solver for MAX/1500. | 479 | 514 | Table~\ref{tbl:gurobi_max_1500} shows the results obtained by the filter solver for MAX/1500. | |
| 480 | 515 | |||
| \renewcommand{\arraystretch}{1.4} | 481 | 516 | \renewcommand{\arraystretch}{1.4} | |
| 482 | 517 | |||
| \begin{table} | 483 | 518 | \begin{table} | |
| \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/500} | 484 | 519 | \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/500} | |
| \label{tbl:gurobi_max_500} | 485 | 520 | \label{tbl:gurobi_max_500} | |
| \centering | 486 | 521 | \centering | |
| {\scalefont{0.77} | 487 | 522 | {\scalefont{0.77} | |
| \begin{tabular}{|c|ccccc|c|c|} | 488 | 523 | \begin{tabular}{|c|ccccc|c|c|} | |
| \hline | 489 | 524 | \hline | |
| $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | 490 | 525 | $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | |
| \hline | 491 | 526 | \hline | |
| 1 & (21, 7, 0) & - & - & - & - & 32~dB & 483 \\ | 492 | 527 | 1 & (21, 7, 0) & - & - & - & - & 32~dB & 483 \\ | |
| 2 & (3, 3, 15) & (31, 9, 0) & - & - & - & 58~dB & 460 \\ | 493 | 528 | 2 & (3, 3, 15) & (31, 9, 0) & - & - & - & 58~dB & 460 \\ | |
| 3 & (3, 3, 15) & (27, 9, 0) & (5, 3, 0) & - & - & 66~dB & 488 \\ | 494 | 529 | 3 & (3, 3, 15) & (27, 9, 0) & (5, 3, 0) & - & - & 66~dB & 488 \\ | |
| 4 & (3, 3, 15) & (19, 7, 0) & (11, 5, 0) & (3, 3, 0) & - & 74~dB & 499 \\ | 495 | 530 | 4 & (3, 3, 15) & (19, 7, 0) & (11, 5, 0) & (3, 3, 0) & - & 74~dB & 499 \\ | |
| 5 & (3, 3, 15) & (23, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 78~dB & 489 \\ | 496 | 531 | 5 & (3, 3, 15) & (23, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 78~dB & 489 \\ | |
| \hline | 497 | 532 | \hline | |
| \end{tabular} | 498 | 533 | \end{tabular} | |
| } | 499 | 534 | } | |
| \end{table} | 500 | 535 | \end{table} | |
| 501 | 536 | |||
| \begin{table} | 502 | 537 | \begin{table} | |
| \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1000} | 503 | 538 | \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1000} | |
| \label{tbl:gurobi_max_1000} | 504 | 539 | \label{tbl:gurobi_max_1000} | |
| \centering | 505 | 540 | \centering | |
| {\scalefont{0.77} | 506 | 541 | {\scalefont{0.77} | |
| \begin{tabular}{|c|ccccc|c|c|} | 507 | 542 | \begin{tabular}{|c|ccccc|c|c|} | |
| \hline | 508 | 543 | \hline | |
| $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | 509 | 544 | $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | |
| \hline | 510 | 545 | \hline | |
| 1 & (37, 11, 0) & - & - & - & - & 56~dB & 999 \\ | 511 | 546 | 1 & (37, 11, 0) & - & - & - & - & 56~dB & 999 \\ | |
| 2 & (3, 3, 15) & (51, 14, 0) & - & - & - & 87~dB & 975 \\ | 512 | 547 | 2 & (3, 3, 15) & (51, 14, 0) & - & - & - & 87~dB & 975 \\ | |
| 3 & (3, 3, 15) & (35, 11, 0) & (19, 7, 0) & - & - & 99~dB & 1000 \\ | 513 | 548 | 3 & (3, 3, 15) & (35, 11, 0) & (19, 7, 0) & - & - & 99~dB & 1000 \\ | |
| 4 & (3, 4, 16) & (27, 8, 0) & (19, 7, 1) & (11, 5, 0) & - & 103~dB & 998 \\ | 514 | 549 | 4 & (3, 4, 16) & (27, 8, 0) & (19, 7, 1) & (11, 5, 0) & - & 103~dB & 998 \\ | |
| 5 & (3, 3, 15) & (31, 9, 0) & (19, 7, 0) & (3, 3, 1) & (3, 3, 0) & 111~dB & 984 \\ | 515 | 550 | 5 & (3, 3, 15) & (31, 9, 0) & (19, 7, 0) & (3, 3, 1) & (3, 3, 0) & 111~dB & 984 \\ | |
| \hline | 516 | 551 | \hline | |
| \end{tabular} | 517 | 552 | \end{tabular} | |
| } | 518 | 553 | } | |
| \end{table} | 519 | 554 | \end{table} | |
| 520 | 555 | |||
| \begin{table} | 521 | 556 | \begin{table} | |
| \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1500} | 522 | 557 | \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MAX/1500} | |
| \label{tbl:gurobi_max_1500} | 523 | 558 | \label{tbl:gurobi_max_1500} | |
| \centering | 524 | 559 | \centering | |
| {\scalefont{0.77} | 525 | 560 | {\scalefont{0.77} | |
| \begin{tabular}{|c|ccccc|c|c|} | 526 | 561 | \begin{tabular}{|c|ccccc|c|c|} | |
| \hline | 527 | 562 | \hline | |
| $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | 528 | 563 | $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | |
| \hline | 529 | 564 | \hline | |
| 1 & (47, 15, 0) & - & - & - & - & 71~dB & 1457 \\ | 530 | 565 | 1 & (47, 15, 0) & - & - & - & - & 71~dB & 1457 \\ | |
| 2 & (19, 6, 15) & (51, 14, 0) & - & - & - & 103~dB & 1489 \\ | 531 | 566 | 2 & (19, 6, 15) & (51, 14, 0) & - & - & - & 103~dB & 1489 \\ | |
| 3 & (3, 3, 15) & (35, 11, 0) & (35, 11, 0) & - & - & 122~dB & 1492 \\ | 532 | 567 | 3 & (3, 3, 15) & (35, 11, 0) & (35, 11, 0) & - & - & 122~dB & 1492 \\ | |
| 4 & (3, 3, 15) & (27, 8, 0) & (19, 7, 0) & (27, 9, 0) & - & 129~dB & 1498 \\ | 533 | 568 | 4 & (3, 3, 15) & (27, 8, 0) & (19, 7, 0) & (27, 9, 0) & - & 129~dB & 1498 \\ | |
| 5 & (3, 3, 15) & (23, 9, 2) & (27, 9, 0) & (19, 7, 0) & (3, 3, 0) & 136~dB & 1499 \\ | 534 | 569 | 5 & (3, 3, 15) & (23, 9, 2) & (27, 9, 0) & (19, 7, 0) & (3, 3, 0) & 136~dB & 1499 \\ | |
| \hline | 535 | 570 | \hline | |
| \end{tabular} | 536 | 571 | \end{tabular} | |
| } | 537 | 572 | } | |
| \end{table} | 538 | 573 | \end{table} | |
| 539 | 574 | |||
| \renewcommand{\arraystretch}{1} | 540 | 575 | \renewcommand{\arraystretch}{1} | |
| 541 | 576 | |||
| From these tables, we can first state that the more stages are used to define | 542 | 577 | From these tables, we can first state that the more stages are used to define | |
| the cascaded FIR filters, the better the rejection. It was an expected result as it has | 543 | 578 | the cascaded FIR filters, the better the rejection. It was an expected result as it has | |
| been previously observed that many small filters are better than | 544 | 579 | been previously observed that many small filters are better than | |
| a single large filter \cite{lim_1988, lim_1996, young_1992}, despite such conclusion | 545 | 580 | a single large filter \cite{lim_1988, lim_1996, young_1992}, despite such conclusions | |
| being hardly used in practice due to the lack of tools for identifying individual filter | 546 | 581 | being hardly used in practice due to the lack of tools for identifying individual filter | |
| coefficients in the cascaded approach. | 547 | 582 | coefficients in the cascaded approach. | |
| 548 | 583 | |||
| Second, the larger the silicon area, the better the rejection. This was also an | 549 | 584 | Second, the larger the silicon area, the better the rejection. This was also an | |
| expected result as more area means a filter of better quality (more coefficients | 550 | 585 | expected result as more area means a filter of better quality with more coefficients | |
| or more bits per coefficient). | 551 | 586 | or more bits per coefficient. | |
| 552 | 587 | |||
| Then, we also observe that the first stage can have a larger shift than the other | 553 | 588 | Then, we also observe that the first stage can have a larger shift than the other | |
| stages. This is explained by the fact that the solver tries to use just enough | 554 | 589 | stages. This is explained by the fact that the solver tries to use just enough | |
| bits for the computed rejection after each stage. In the first stage, a | 555 | 590 | bits for the computed rejection after each stage. In the first stage, a | |
| balance between a strong rejection with a low number of bits is targeted. Equation~\ref{eq:maxshift} | 556 | 591 | balance between a strong rejection with a low number of bits is targeted. Equation~\ref{eq:maxshift} | |
| gives the relation between both values. | 557 | 592 | gives the relation between both values. | |
| 558 | 593 | |||
| Finally, we note that the solver consumes all the given silicon area. | 559 | 594 | Finally, we note that the solver consumes all the given silicon area. | |
| 560 | 595 | |||
| The following graphs present the rejection for real data on the FPGA. In all following | 561 | 596 | The following graphs present the rejection for real data on the FPGA. In all the following | |
| figures, the solid line represents the actual rejection of the filtered | 562 | 597 | figures, the solid line represents the actual rejection of the filtered | |
| data on the FPGA as measured experimentally and the dashed line are the noise level | 563 | 598 | data on the FPGA as measured experimentally and the dashed line are the noise levels | |
| given by the quadratic solver. The configurations are those computed in the previous section. | 564 | 599 | given by the quadratic solver. The configurations are those computed in the previous section. | |
| 565 | 600 | |||
| Figure~\ref{fig:max_500_result} shows the rejection of the different configurations in the case of MAX/500. | 566 | 601 | Figure~\ref{fig:max_500_result} shows the rejection of the different configurations in the case of MAX/500. | |
| Figure~\ref{fig:max_1000_result} shows the rejection of the different configurations in the case of MAX/1000. | 567 | 602 | Figure~\ref{fig:max_1000_result} shows the rejection of the different configurations in the case of MAX/1000. | |
| Figure~\ref{fig:max_1500_result} shows the rejection of the different configurations in the case of MAX/1500. | 568 | 603 | Figure~\ref{fig:max_1500_result} shows the rejection of the different configurations in the case of MAX/1500. | |
| 569 | 604 | |||
| \begin{figure} | 570 | 605 | \begin{figure} | |
| \centering | 571 | 606 | \centering | |
| \includegraphics[width=\linewidth]{images/max_500} | 572 | 607 | \includegraphics[width=\linewidth]{images/max_500} | |
| \caption{Signal spectrum for MAX/500} | 573 | 608 | \caption{Signal spectrum for MAX/500} | |
| \label{fig:max_500_result} | 574 | 609 | \label{fig:max_500_result} | |
| \end{figure} | 575 | 610 | \end{figure} | |
| 576 | 611 | |||
| \begin{figure} | 577 | 612 | \begin{figure} | |
| \centering | 578 | 613 | \centering | |
| \includegraphics[width=\linewidth]{images/max_1000} | 579 | 614 | \includegraphics[width=\linewidth]{images/max_1000} | |
| \caption{Signal spectrum for MAX/1000} | 580 | 615 | \caption{Signal spectrum for MAX/1000} | |
| \label{fig:max_1000_result} | 581 | 616 | \label{fig:max_1000_result} | |
| \end{figure} | 582 | 617 | \end{figure} | |
| 583 | 618 | |||
| \begin{figure} | 584 | 619 | \begin{figure} | |
| \centering | 585 | 620 | \centering | |
| \includegraphics[width=\linewidth]{images/max_1500} | 586 | 621 | \includegraphics[width=\linewidth]{images/max_1500} | |
| \caption{Signal spectrum for MAX/1500} | 587 | 622 | \caption{Signal spectrum for MAX/1500} | |
| \label{fig:max_1500_result} | 588 | 623 | \label{fig:max_1500_result} | |
| \end{figure} | 589 | 624 | \end{figure} | |
| 590 | 625 | |||
| In all cases, we observe that the actual rejection is close to the rejection computed by the solver. | 591 | 626 | In all cases, we observe that the actual rejection is close to the rejection computed by the solver. | |
| 592 | 627 | |||
| We compare the actual silicon resources given by Vivado to the | 593 | 628 | We compare the actual silicon resources given by Vivado to the | |
| resources in arbitrary units. | 594 | 629 | resources in arbitrary units. | |
| The goal is to check that our arbitrary units of silicon area models well enough | 595 | 630 | The goal is to check that our arbitrary units of silicon area models well enough | |
| the real resources on the FPGA. Especially we want to verify that, for a given | 596 | 631 | the real resources on the FPGA. Especially we want to verify that, for a given | |
| number of arbitrary units, the actual silicon resources do not depend on the | 597 | 632 | number of arbitrary units, the actual silicon resources do not depend on the | |
| number of stages $n$. Most significantly, our approach aims | 598 | 633 | number of stages $n$. Most significantly, our approach aims | |
| at remaining far enough from the practical logic gate implementation used by | 599 | 634 | at remaining far enough from the practical logic gate implementation used by | |
| various vendors to remain platform independent and be portable from one | 600 | 635 | various vendors to remain platform independent and be portable from one | |
| architecture to another. | 601 | 636 | architecture to another. | |
| 602 | 637 | |||
| Table~\ref{tbl:resources_usage} shows the resources usage in the case of MAX/500, MAX/1000 and | 603 | 638 | Table~\ref{tbl:resources_usage} shows the resources usage in the case of MAX/500, MAX/1000 and | |
| MAX/1500 \emph{i.e.} when the maximum allowed silicon area is fixed to 500, 1000 | 604 | 639 | MAX/1500 \emph{i.e.} when the maximum allowed silicon area is fixed to 500, 1000 | |
| and 1500 arbitrary units. We have taken care to extract solely the resources used by | 605 | 640 | and 1500 arbitrary units. We have taken care to extract solely the resources used by | |
| the FIR filters and remove additional processing blocks including FIFO and PL to | 606 | 641 | the FIR filters and remove additional processing blocks including FIFO and Programmable | |
| PS communication. | 607 | 642 | Logic (PL -- FPGA) to Processing System (PS -- general purpose processor) communication. | |
| 608 | 643 | |||
| \begin{table} | 609 | 644 | \begin{table}[h!tb] | |
| \caption{Resource occupation. The last column refers to available resources on a Zynq-7010 as found on the Redpitaya.} | 610 | 645 | \caption{Resource occupation. The last column refers to available resources on a Zynq-7010 as found on the Redpitaya.} | |
| \label{tbl:resources_usage} | 611 | 646 | \label{tbl:resources_usage} | |
| \centering | 612 | 647 | \centering | |
| \begin{tabular}{|c|c|ccc|c|} | 613 | 648 | \begin{tabular}{|c|c|ccc|c|} | |
| \hline | 614 | 649 | \hline | |
| $n$ & & MAX/500 & MAX/1000 & MAX/1500 & \emph{Zynq 7010} \\ \hline\hline | 615 | 650 | $n$ & & MAX/500 & MAX/1000 & MAX/1500 & \emph{Zynq 7010} \\ \hline\hline | |
| & LUT & 249 & 453 & 627 & \emph{17600} \\ | 616 | 651 | & LUT & 249 & 453 & 627 & \emph{17600} \\ | |
| 1 & BRAM & 1 & 1 & 1 & \emph{120} \\ | 617 | 652 | 1 & BRAM & 1 & 1 & 1 & \emph{120} \\ | |
| & DSP & 21 & 37 & 47 & \emph{80} \\ \hline | 618 | 653 | & DSP & 21 & 37 & 47 & \emph{80} \\ \hline | |
| & LUT & 2374 & 5494 & 691 & \emph{17600} \\ | 619 | 654 | & LUT & 2374 & 5494 & 691 & \emph{17600} \\ | |
| 2 & BRAM & 2 & 2 & 2 & \emph{120} \\ | 620 | 655 | 2 & BRAM & 2 & 2 & 2 & \emph{120} \\ | |
| & DSP & 0 & 0 & 70 & \emph{80} \\ \hline | 621 | 656 | & DSP & 0 & 0 & 70 & \emph{80} \\ \hline | |
| & LUT & 2443 & 3304 & 3521 & \emph{17600} \\ | 622 | 657 | & LUT & 2443 & 3304 & 3521 & \emph{17600} \\ | |
| 3 & BRAM & 3 & 3 & 3 & \emph{120} \\ | 623 | 658 | 3 & BRAM & 3 & 3 & 3 & \emph{120} \\ | |
| & DSP & 0 & 19 & 35 & \emph{80} \\ \hline | 624 | 659 | & DSP & 0 & 19 & 35 & \emph{80} \\ \hline | |
| & LUT & 2634 & 3753 & 2557 & \emph{17600} \\ | 625 | 660 | & LUT & 2634 & 3753 & 2557 & \emph{17600} \\ | |
| 4 & BRAM & 4 & 4 & 4 & \emph{120} \\ | 626 | 661 | 4 & BRAM & 4 & 4 & 4 & \emph{120} \\ | |
| & DPS & 0 & 19 & 46 & \emph{80} \\ \hline | 627 | 662 | & DPS & 0 & 19 & 46 & \emph{80} \\ \hline | |
| & LUT & 2423 & 3047 & 2847 & \emph{17600} \\ | 628 | 663 | & LUT & 2423 & 3047 & 2847 & \emph{17600} \\ | |
| 5 & BRAM & 5 & 5 & 5 & \emph{120} \\ | 629 | 664 | 5 & BRAM & 5 & 5 & 5 & \emph{120} \\ | |
| & DPS & 0 & 22 & 46 & \emph{80} \\ \hline | 630 | 665 | & DPS & 0 & 22 & 46 & \emph{80} \\ \hline | |
| \end{tabular} | 631 | 666 | \end{tabular} | |
| \end{table} | 632 | 667 | \end{table} | |
| 633 | 668 | |||
| In some cases, Vivado replaces the DSPs by Look Up Tables (LUTs). We assume that, | 634 | 669 | In some cases, Vivado replaces the DSPs by Look Up Tables (LUTs). We assume that, | |
| when the filters coefficients are small enough, or when the input size is small | 635 | 670 | when the filter coefficients are small enough, or when the input size is small | |
| enough, Vivado optimized resource consumption by selecting multiplexers to | 636 | 671 | enough, Vivado optimizes resource consumption by selecting multiplexers to | |
| implement the multiplications instead of a DSP. In this case, it is quite difficult | 637 | 672 | implement the multiplications instead of a DSP. In this case, it is quite difficult | |
| to compare the whole silicon budget. | 638 | 673 | to compare the whole silicon budget. | |
| 639 | 674 | |||
| However, a rough estimation can be made with a simple equivalence. Looking at | 640 | 675 | However, a rough estimation can be made with a simple equivalence: looking at | |
| the first column (MAX/500), where the number of LUTs is quite stable for $n \geq 2$, | 641 | 676 | the first column (MAX/500), where the number of LUTs is quite stable for $n \geq 2$, | |
| we can deduce that a DSP is roughly equivalent to 100~LUTs in terms of silicon | 642 | 677 | we can deduce that a DSP is roughly equivalent to 100~LUTs in terms of silicon | |
| area use. With this equivalence, our 500 arbitraty units corresponds to 2500 LUTs, | 643 | 678 | area use. With this equivalence, our 500 arbitraty units correspond to 2500 LUTs, | |
| 1000 arbitrary units corresponds to 5000 LUTs and 1500 arbitrary units corresponds | 644 | 679 | 1000 arbitrary units correspond to 5000 LUTs and 1500 arbitrary units correspond | |
| to 7300 LUTs. The conclusion is that the orders of magnitude of our arbitrary | 645 | 680 | to 7300 LUTs. The conclusion is that the orders of magnitude of our arbitrary | |
| unit are quite good. The relatively small differences can probably be explained | 646 | 681 | unit map well to actual hardware resources. The relatively small differences can probably be explained | |
| by the optimizations done by Vivado based on the detailed map of available processing resources. | 647 | 682 | by the optimizations done by Vivado based on the detailed map of available processing resources. | |
| 648 | 683 | |||
| We present the computation time to solve the quadratic problem. | 649 | 684 | We now present the computation time needed to solve the quadratic problem. | |
| For each case, the filter solver software are executed with a Intel(R) Xeon(R) CPU E5606 | 650 | 685 | For each case, the filter solver software is executed on a Intel(R) Xeon(R) CPU E5606 | |
| cadenced at 2.13~GHz. The CPU has 8 cores that are used by Gurobi to solve | 651 | 686 | clocked at 2.13~GHz. The CPU has 8 cores that are used by Gurobi to solve | |
| the quadratic problem. | 652 | 687 | the quadratic problem. Table~\ref{tbl:area_time} shows the time needed to solve the quadratic | |
| 653 | ||||
| Table~\ref{tbl:area_time} shows the time needed to solve the quadratic | 654 | |||
| problem when the maximal area is fixed to 500, 1000 and 1500 arbitrary units. | 655 | 688 | problem when the maximal area is fixed to 500, 1000 and 1500 arbitrary units. | |
| 656 | 689 | |||
| \begin{table} | 657 | 690 | \begin{table}[h!tb] | |
| \caption{Time to solve the quadratic program with Gurobi} | 658 | 691 | \caption{Time needed to solve the quadratic program with Gurobi} | |
| \label{tbl:area_time} | 659 | 692 | \label{tbl:area_time} | |
| \centering | 660 | 693 | \centering | |
| \begin{tabular}{|c|c|c|c|}\hline | 661 | 694 | \begin{tabular}{|c|c|c|c|}\hline | |
| $n$ & Time (MAX/500) & Time (MAX/1000) & Time (MAX/1500) \\\hline\hline | 662 | 695 | $n$ & Time (MAX/500) & Time (MAX/1000) & Time (MAX/1500) \\\hline\hline | |
| 1 & 0.1~s & 0.1~s & 0.3~s \\ | 663 | 696 | 1 & 0.1~s & 0.1~s & 0.3~s \\ | |
| 2 & 1.1~s & 2.2~s & 12~s \\ | 664 | 697 | 2 & 1.1~s & 2.2~s & 12~s \\ | |
| 3 & 17~s & 137~s ($\approx$ 2~min) & 275~s ($\approx$ 4~min) \\ | 665 | 698 | 3 & 17~s & 137~s ($\approx$ 2~min) & 275~s ($\approx$ 4~min) \\ | |
| 4 & 52~s & 5448~s ($\approx$ 90~min) & 5505~s ($\approx$ 17~h) \\ | 666 | 699 | 4 & 52~s & 5448~s ($\approx$ 90~min) & 5505~s ($\approx$ 17~h) \\ | |
| 5 & 286~s ($\approx$ 4~min) & 4119~s ($\approx$ 68~min) & 235479~s ($\approx$ 3~days) \\\hline | 667 | 700 | 5 & 286~s ($\approx$ 4~min) & 4119~s ($\approx$ 68~min) & 235479~s ($\approx$ 3~days) \\\hline | |
| \end{tabular} | 668 | 701 | \end{tabular} | |
| \end{table} | 669 | 702 | \end{table} | |
| 670 | 703 | |||
| As expected, the computation time seems to rise exponentially with the number of stages. % TODO: exponentiel ? | 671 | 704 | As expected, the computation time seems to rise exponentially with the number of stages. % TODO: exponentiel ? | |
| When the area is limited, the design exploration space is more limited and the solver is able to | 672 | 705 | When the area is limited, the design exploration space is more limited and the solver is able to | |
| find an optimal solution faster. On the contrary, in the case of MAX/1500 with | 673 | 706 | find an optimal solution faster. On the contrary, in the case of MAX/1500 with | |
| 5~stages, we were not able to obtain a result after 40~hours of computation so we decided to stop. | 674 | 707 | 5~stages, we were not able to obtain a result after 40~hours of computation when the program was | |
| 708 | manually stopped. | |||
| 675 | 709 | |||
| \section{Experiments with fixed rejection target} | 676 | 710 | \subsection{Minimizing resource occupation at fixed rejection}\label{sec:fixed_rej} | |
| \label{sec:fixed_rej} | 677 | |||
| This section presents the results of complementary quadratic program which we | 678 | |||
| minimize the area occupation for a targeted noise level. | 679 | |||
| 680 | 711 | |||
| 712 | This section presents the results of the complementary quadratic program aimed at | |||
| 713 | minimizing the area occupation for a targeted rejection level. | |||
| 714 | ||||
| The experimental setup is also composed of three cases. The raw input is the same | 681 | 715 | The experimental setup is also composed of three cases. The raw input is the same | |
| as previous section, a PRN generator, which fixes the input data size $\Pi^I$. | 682 | 716 | as in the previous section, from a PRN generator, which fixes the input data size $\Pi^I$. | |
| Then the targeted rejection $\mathcal{R}$ has been fixed to either 40, 60 or 80~dB. | 683 | 717 | Then the targeted rejection $\mathcal{R}$ has been fixed to either 40, 60 or 80~dB. | |
| Hence, the three cases have been named: MIN/40, MIN/60, MIN/80. | 684 | 718 | Hence, the three cases have been named: MIN/40, MIN/60, MIN/80. | |
| The number of configurations $p$ is the same as previous section. | 685 | 719 | The number of configurations $p$ is the same as previous section. | |
| 686 | 720 | |||
| Table~\ref{tbl:gurobi_min_40} shows the results obtained by the filter solver for MIN/40. | 687 | 721 | Table~\ref{tbl:gurobi_min_40} shows the results obtained by the filter solver for MIN/40. | |
| Table~\ref{tbl:gurobi_min_60} shows the results obtained by the filter solver for MIN/60. | 688 | 722 | Table~\ref{tbl:gurobi_min_60} shows the results obtained by the filter solver for MIN/60. | |
| Table~\ref{tbl:gurobi_min_80} shows the results obtained by the filter solver for MIN/80. | 689 | 723 | Table~\ref{tbl:gurobi_min_80} shows the results obtained by the filter solver for MIN/80. | |
| 690 | 724 | |||
| \renewcommand{\arraystretch}{1.4} | 691 | 725 | \renewcommand{\arraystretch}{1.4} | |
| 692 | 726 | |||
| \begin{table} | 693 | 727 | \begin{table}[h!tb] | |
| \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/40} | 694 | 728 | \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/40} | |
| \label{tbl:gurobi_min_40} | 695 | 729 | \label{tbl:gurobi_min_40} | |
| \centering | 696 | 730 | \centering | |
| {\scalefont{0.77} | 697 | 731 | {\scalefont{0.77} | |
| \begin{tabular}{|c|ccccc|c|c|} | 698 | 732 | \begin{tabular}{|c|ccccc|c|c|} | |
| \hline | 699 | 733 | \hline | |
| $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | 700 | 734 | $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | |
| \hline | 701 | 735 | \hline | |
| 1 & (27, 8, 0) & - & - & - & - & 41~dB & 648 \\ | 702 | 736 | 1 & (27, 8, 0) & - & - & - & - & 41~dB & 648 \\ | |
| 2 & (3, 2, 14) & (19, 7, 0) & - & - & - & 40~dB & 263 \\ | 703 | 737 | 2 & (3, 2, 14) & (19, 7, 0) & - & - & - & 40~dB & 263 \\ | |
| 3 & (3, 3, 15) & (11, 5, 0) & (3, 3, 0) & - & - & 41~dB & 192 \\ | 704 | 738 | 3 & (3, 3, 15) & (11, 5, 0) & (3, 3, 0) & - & - & 41~dB & 192 \\ | |
| 4 & (3, 3, 15) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & - & 42~dB & 147 \\ | 705 | 739 | 4 & (3, 3, 15) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & - & 42~dB & 147 \\ | |
| \hline | 706 | 740 | \hline | |
| \end{tabular} | 707 | 741 | \end{tabular} | |
| } | 708 | 742 | } | |
| \end{table} | 709 | 743 | \end{table} | |
| 710 | 744 | |||
| \begin{table} | 711 | 745 | \begin{table}[h!tb] | |
| \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/60} | 712 | 746 | \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/60} | |
| \label{tbl:gurobi_min_60} | 713 | 747 | \label{tbl:gurobi_min_60} | |
| \centering | 714 | 748 | \centering | |
| {\scalefont{0.77} | 715 | 749 | {\scalefont{0.77} | |
| \begin{tabular}{|c|ccccc|c|c|} | 716 | 750 | \begin{tabular}{|c|ccccc|c|c|} | |
| \hline | 717 | 751 | \hline | |
| $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | 718 | 752 | $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | |
| \hline | 719 | 753 | \hline | |
| 1 & (39, 13, 0) & - & - & - & - & 60~dB & 1131 \\ | 720 | 754 | 1 & (39, 13, 0) & - & - & - & - & 60~dB & 1131 \\ | |
| 2 & (3, 3, 15) & (35, 10, 0) & - & - & - & 60~dB & 547 \\ | 721 | 755 | 2 & (3, 3, 15) & (35, 10, 0) & - & - & - & 60~dB & 547 \\ | |
| 3 & (3, 3, 15) & (27, 8, 0) & (3, 3, 0) & - & - & 62~dB & 426 \\ | 722 | 756 | 3 & (3, 3, 15) & (27, 8, 0) & (3, 3, 0) & - & - & 62~dB & 426 \\ | |
| 4 & (3, 2, 14) & (11, 5, 1) & (11, 5, 0) & (3, 3, 0) & - & 60~dB & 344 \\ | 723 | 757 | 4 & (3, 2, 14) & (11, 5, 1) & (11, 5, 0) & (3, 3, 0) & - & 60~dB & 344 \\ | |
| 5 & (3, 2, 14) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & 60~dB & 279 \\ | 724 | 758 | 5 & (3, 2, 14) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & (3, 3, 0) & 60~dB & 279 \\ | |
| \hline | 725 | 759 | \hline | |
| \end{tabular} | 726 | 760 | \end{tabular} | |
| } | 727 | 761 | } | |
| \end{table} | 728 | 762 | \end{table} | |
| 729 | 763 | |||
| \begin{table} | 730 | 764 | \begin{table}[h!tb] | |
| \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/80} | 731 | 765 | \caption{Configurations $(C_i, \pi_i^C, \pi_i^S)$, rejections and areas (in arbitrary units) for MIN/80} | |
| \label{tbl:gurobi_min_80} | 732 | 766 | \label{tbl:gurobi_min_80} | |
| \centering | 733 | 767 | \centering | |
| {\scalefont{0.77} | 734 | 768 | {\scalefont{0.77} | |
| \begin{tabular}{|c|ccccc|c|c|} | 735 | 769 | \begin{tabular}{|c|ccccc|c|c|} | |
| \hline | 736 | 770 | \hline | |
| $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | 737 | 771 | $n$ & $i = 1$ & $i = 2$ & $i = 3$ & $i = 4$ & $i = 5$ & Rejection & Area \\ | |
| \hline | 738 | 772 | \hline | |
| 1 & (55, 16, 0) & - & - & - & - & 81~dB & 1760 \\ | 739 | 773 | 1 & (55, 16, 0) & - & - & - & - & 81~dB & 1760 \\ | |
| 2 & (3, 3, 15) & (47, 14, 0) & - & - & - & 80~dB & 903 \\ | 740 | 774 | 2 & (3, 3, 15) & (47, 14, 0) & - & - & - & 80~dB & 903 \\ | |
| 3 & (3, 3, 15) & (23, 9, 0) & (19, 7, 0) & - & - & 80~dB & 698 \\ | 741 | 775 | 3 & (3, 3, 15) & (23, 9, 0) & (19, 7, 0) & - & - & 80~dB & 698 \\ | |
| 4 & (3, 3, 15) & (27, 9, 0) & (7, 7, 4) & (3, 3, 0) & - & 80~dB & 605 \\ | 742 | 776 | 4 & (3, 3, 15) & (27, 9, 0) & (7, 7, 4) & (3, 3, 0) & - & 80~dB & 605 \\ | |
| 5 & (3, 2, 14) & (27, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 81~dB & 534 \\ | 743 | 777 | 5 & (3, 2, 14) & (27, 8, 0) & (3, 3, 1) & (3, 3, 0) & (3, 3, 0) & 81~dB & 534 \\ | |
| \hline | 744 | 778 | \hline | |
| \end{tabular} | 745 | 779 | \end{tabular} | |
| } | 746 | 780 | } | |
| \end{table} | 747 | 781 | \end{table} | |
| \renewcommand{\arraystretch}{1} | 748 | 782 | \renewcommand{\arraystretch}{1} | |
| 749 | 783 | |||
| From these tables, we can first state that all configuration reach the target rejection | 750 | 784 | % JMF : je croyais que dans un cas le monolithique n'y arrivait juste pas : tu as retire' ce cas ? | |
| level and more we have stages lesser is the area occupied in arbitrary unit. | 751 | 785 | From these tables, we can first state that all configurations reach the targeted rejection | |
| Futhermore, the area of the monolithic filter is twice bigger than the two cascaded. | 752 | 786 | level or even better thanks to our underestimate of the cascade rejection as the sum of the | |
| More generally, more there is filters lower is the occupied area. | 753 | 787 | individual filter rejection | |
| 788 | % we have stages lesser is the area occupied in arbitrary unit. JMF : je ne comprends pas cette phrase | |||
| 789 | Futhermore, the area of the monolithic filter is twice as big as the two cascaded filters | |||
| 790 | (1131 and 1760 arbitrary units v.s 547 and 903 arbitrary units for 60 and 80~dB rejection | |||
| 791 | respectively). More generally, the more filters are cascaded, the lower the occupied area. | |||
| 754 | 792 | |||
| Like in previous section, the solver choose always a little filter as first | 755 | 793 | Like in previous section, the solver chooses always a little filter as first | |
| filter stage and the second one is often the biggest filter. this choice can be explain | 756 | 794 | filter stage and the second one is often the biggest filter. This choice can be explained | |
| as the previous section. The solver uses just enough bits to not degrade the input | 757 | 795 | as in the previous section, with the solver using just enough bits not to degrade the input | |
| signal and in second filter it can choose a better filter to improve rejection without | 758 | 796 | signal and in the second filter selecting a better filter to improve rejection without | |
| have too bits in the output data. | 759 | 797 | having too many bits in the output data. | |
| 760 | 798 | |||
| For the specific case in MIN/40 for $n = 5$ the solver has determined that the optimal | 761 | 799 | For the specific case of MIN/40 for $n = 5$ the solver has determined that the optimal | |
| number of filter is 4 so it not chose any configuration in last filter. Hence this | 762 | 800 | number of filters is 4 so it did not chose any configuration for the last filter. Hence this | |
| solution is equivalent to the result for $n = 4$. | 763 | 801 | solution is equivalent to the result for $n = 4$. | |
| 764 | 802 | |||
| The following graphs present the rejection for real data on the FPGA. In all following | 765 | 803 | The following graphs present the rejection for real data on the FPGA. In all the following | |
| figures, the solid line represents the actual rejection of the filtered | 766 | 804 | figures, the solid line represents the actual rejection of the filtered | |
| data on the FPGA as measured experimentally and the dashed line are the noise level | 767 | 805 | data on the FPGA as measured experimentally and the dashed line is the noise level | |
| given by the quadratic solver. | 768 | 806 | given by the quadratic solver. | |
| 769 | 807 | |||
| Figure~\ref{fig:min_40} shows the rejection of the different configurations in the case of MIN/40. | 770 | 808 | Figure~\ref{fig:min_40} shows the rejection of the different configurations in the case of MIN/40. | |
| Figure~\ref{fig:min_60} shows the rejection of the different configurations in the case of MIN/60. | 771 | 809 | Figure~\ref{fig:min_60} shows the rejection of the different configurations in the case of MIN/60. | |
| Figure~\ref{fig:min_80} shows the rejection of the different configurations in the case of MIN/80. | 772 | 810 | Figure~\ref{fig:min_80} shows the rejection of the different configurations in the case of MIN/80. | |
| 773 | 811 | |||
| \begin{figure} | 774 | 812 | \begin{figure} | |
| \centering | 775 | 813 | \centering | |
| \includegraphics[width=\linewidth]{images/min_40} | 776 | 814 | \includegraphics[width=\linewidth]{images/min_40} | |
| \caption{Signal spectrum for MIN/40} | 777 | 815 | \caption{Signal spectrum for MIN/40} | |
| \label{fig:min_40} | 778 | 816 | \label{fig:min_40} | |
| \end{figure} | 779 | 817 | \end{figure} | |
| 780 | 818 | |||
| \begin{figure} | 781 | 819 | \begin{figure} | |
| \centering | 782 | 820 | \centering | |
| \includegraphics[width=\linewidth]{images/min_60} | 783 | 821 | \includegraphics[width=\linewidth]{images/min_60} | |
| \caption{Signal spectrum for MIN/60} | 784 | 822 | \caption{Signal spectrum for MIN/60} | |
| \label{fig:min_60} | 785 | 823 | \label{fig:min_60} | |
| \end{figure} | 786 | 824 | \end{figure} | |
| 787 | 825 | |||
| \begin{figure} | 788 | 826 | \begin{figure} | |
| \centering | 789 | 827 | \centering | |
| \includegraphics[width=\linewidth]{images/min_80} | 790 | 828 | \includegraphics[width=\linewidth]{images/min_80} | |
| \caption{Signal spectrum for MIN/80} | 791 | 829 | \caption{Signal spectrum for MIN/80} | |
| \label{fig:min_80} | 792 | 830 | \label{fig:min_80} | |
| \end{figure} | 793 | 831 | \end{figure} | |
| 794 | 832 | |||
| We observe that all rejections given by the quadratic solver are close to the real | 795 | 833 | We observe that all rejections given by the quadratic solver are close to the experimentally | |
| rejection. All curves prove that the constraint to reach the target rejection is | 796 | 834 | measured rejection. All curves prove that the constraint to reach the target rejection is | |
| respected both monolithic filter or cascaded filters. | 797 | 835 | respected with both monolithic or cascaded filters. | |
| 798 | 836 | |||
| Table~\ref{tbl:resources_usage} shows the resources usage in the case of MIN/40, MIN/60 and | 799 | 837 | Table~\ref{tbl:resources_usage} shows the resource usage in the case of MIN/40, MIN/60 and | |
| MIN/80 \emph{i.e.} when the target rejection is fixed to 40, 60 and 80~dB. We | 800 | 838 | MIN/80 \emph{i.e.} when the target rejection is fixed to 40, 60 and 80~dB. We | |
| have taken care to extract solely the resources used by | 801 | 839 | have taken care to extract solely the resources used by | |
| the FIR filters and remove additional processing blocks including FIFO and PL to | 802 | 840 | the FIR filters and remove additional processing blocks including FIFO and PL to | |
| PS communication. | 803 | 841 | PS communication. | |
| 804 | 842 | |||
| \begin{table} | 805 | 843 | \begin{table} | |
| \caption{Resource occupation. The last column refers to available resources on a Zynq-7010 as found on the Redpitaya.} | 806 | 844 | \caption{Resource occupation. The last column refers to available resources on a Zynq-7010 as found on the Redpitaya.} | |
| \label{tbl:resources_usage_comp} | 807 | 845 | \label{tbl:resources_usage_comp} | |
| \centering | 808 | 846 | \centering | |
| \begin{tabular}{|c|c|ccc|c|} | 809 | 847 | \begin{tabular}{|c|c|ccc|c|} | |
| \hline | 810 | 848 | \hline | |
| $n$ & & MIN/40 & MIN/60 & MIN/80 & \emph{Zynq 7010} \\ \hline\hline | 811 | 849 | $n$ & & MIN/40 & MIN/60 & MIN/80 & \emph{Zynq 7010} \\ \hline\hline | |
| & LUT & 343 & 334 & 772 & \emph{17600} \\ | 812 | 850 | & LUT & 343 & 334 & 772 & \emph{17600} \\ | |
| 1 & BRAM & 1 & 1 & 1 & \emph{120} \\ | 813 | 851 | 1 & BRAM & 1 & 1 & 1 & \emph{120} \\ | |
| & DSP & 27 & 39 & 55 & \emph{80} \\ \hline | 814 | 852 | & DSP & 27 & 39 & 55 & \emph{80} \\ \hline | |
| & LUT & 1252 & 2862 & 5099 & \emph{17600} \\ | 815 | 853 | & LUT & 1252 & 2862 & 5099 & \emph{17600} \\ | |
| 2 & BRAM & 2 & 2 & 2 & \emph{120} \\ | 816 | 854 | 2 & BRAM & 2 & 2 & 2 & \emph{120} \\ | |
| & DSP & 0 & 0 & 0 & \emph{80} \\ \hline | 817 | 855 | & DSP & 0 & 0 & 0 & \emph{80} \\ \hline | |
| & LUT & 891 & 2148 & 2023 & \emph{17600} \\ | 818 | 856 | & LUT & 891 & 2148 & 2023 & \emph{17600} \\ | |
| 3 & BRAM & 3 & 3 & 3 & \emph{120} \\ | 819 | 857 | 3 & BRAM & 3 & 3 & 3 & \emph{120} \\ | |
| & DSP & 0 & 0 & 19 & \emph{80} \\ \hline | 820 | 858 | & DSP & 0 & 0 & 19 & \emph{80} \\ \hline | |
| & LUT & 662 & 1729 & 2451 & \emph{17600} \\ | 821 | 859 | & LUT & 662 & 1729 & 2451 & \emph{17600} \\ | |
| 4 & BRAM & 4 & 4 & 4 & \emph{120} \\ | 822 | 860 | 4 & BRAM & 4 & 4 & 4 & \emph{120} \\ | |
| & DPS & 0 & 0 & 7 & \emph{80} \\ \hline | 823 | 861 | & DPS & 0 & 0 & 7 & \emph{80} \\ \hline | |
| & LUT & - & 1259 & 2602 & \emph{17600} \\ | 824 | 862 | & LUT & - & 1259 & 2602 & \emph{17600} \\ | |
| 5 & BRAM & - & 5 & 5 & \emph{120} \\ | 825 | 863 | 5 & BRAM & - & 5 & 5 & \emph{120} \\ | |
| & DPS & - & 0 & 0 & \emph{80} \\ \hline | 826 | 864 | & DPS & - & 0 & 0 & \emph{80} \\ \hline | |
| \end{tabular} | 827 | 865 | \end{tabular} | |
| \end{table} | 828 | 866 | \end{table} | |
| 829 | 867 | |||
| If we keep the previous estimation of cost of one DSP in term of LUT (1 DSP $\approx$ 100 LUT) | 830 | 868 | If we keep the previous estimation of cost of one DSP in terms of LUT (1 DSP $\approx$ 100 LUT) | |
| the real resource consumption decrease in function of number of stage filter according | 831 | 869 | the real resource consumption decreases as a function of the number of stages in the cascaded | |
| 870 | filter according | |||
| to the solution given by the quadratic solver. Indeed, we have always a decreasing | 832 | 871 | to the solution given by the quadratic solver. Indeed, we have always a decreasing | |
| consumption even if the difference between the monolithic and the two cascaded | 833 | 872 | consumption even if the difference between the monolithic and the two cascaded | |
| filters is lesser than expected. | 834 | 873 | filters is less than expected. | |
| 835 | 874 | |||
| Finally, the table~\ref{tbl:area_time_comp} shows the computation time to solve | 836 | 875 | Finally, table~\ref{tbl:area_time_comp} shows the computation time to solve | |
| the quadratic program. | 837 | 876 | the quadratic program. | |
| 838 | 877 | |||
| \begin{table} | 839 | 878 | \begin{table}[h!tb] | |
| \caption{Time to solve the quadratic program with Gurobi} | 840 | 879 | \caption{Time to solve the quadratic program with Gurobi} | |
| \label{tbl:area_time_comp} | 841 | 880 | \label{tbl:area_time_comp} | |
| \centering | 842 | 881 | \centering | |
| \begin{tabular}{|c|c|c|c|}\hline | 843 | 882 | \begin{tabular}{|c|c|c|c|}\hline | |
| $n$ & Time (MIN/40) & Time (MIN/60) & Time (MIN/80) \\\hline\hline | 844 | 883 | $n$ & Time (MIN/40) & Time (MIN/60) & Time (MIN/80) \\\hline\hline | |
| 1 & 0.07~s & 0.02~s & 0.01~s \\ | 845 | 884 | 1 & 0.07~s & 0.02~s & 0.01~s \\ | |
| 2 & 7.8~s & 16~s & 14~s \\ | 846 | 885 | 2 & 7.8~s & 16~s & 14~s \\ | |
| 3 & 4.7~s & 14~s & 28~s \\ | 847 | 886 | 3 & 4.7~s & 14~s & 28~s \\ | |
| 4 & 39~s & 20~s & 193~s \\ | 848 | 887 | 4 & 39~s & 20~s & 193~s \\ | |
| 5 & 126~s & 12~s & 170~s \\\hline | 849 | 888 | 5 & 126~s & 12~s & 170~s \\\hline | |
| \end{tabular} | 850 | 889 | \end{tabular} | |
| \end{table} | 851 | 890 | \end{table} | |
| 852 | 891 | |||
| The time needed to solve this configuration are substantially faster than time | 853 | 892 | The time needed to solve this configuration is significantly shorter than the time | |
| needed in the previous section. Indeed the worst time in this case is only 3~minutes | 854 | 893 | needed in the previous section. Indeed the worst time in this case is only 3~minutes, | |
| in balance of 3~days on previous section. We are able to solve more easily this | 855 | 894 | compared to 3~days in the previous section: this problem is more easily solved than the | |
| problem than the previous one. | 856 | 895 | previous one. | |
| 857 | 896 | |||
| \section{Conclusion} | 858 | 897 | \section{Conclusion} | |
| 859 | 898 | |||
| In this paper, we have proposed a new approach to work with a cascade of FIR filter inside a FPGA. | 860 | 899 | We have proposed a new approach to schedule a set of signal processing blocks whose performances | |
| This method aims to be hardware independent and focus an high-level of abstraction. | 861 | 900 | and resource consumption has been tabulated, and applied this methodology to the practical | |
| We have modeled the FIR filter operation and the data shift impact. With this model | 862 | 901 | case of implementing cascaded FIR filters inside a FPGA. | |
| we have created a quadratic program to select the optimal FIR coefficient set to reject a | 863 | 902 | This method aims to be hardware independent and focuses an a high-level of abstraction. | |
| maximum of noise. In our experiments we have chosen deliberately some common tools | 864 | 903 | We have modeled the FIR filter operation and the impact of data shift. Thanks to this model, | |
| to design the filter coefficients but we can use any other method. | 865 | 904 | we have created a quadratic program to select the optimal FIR taps to reach a targeted | |
| 905 | rejection. Individual filter taps have been identified using commonly available tools and the | |||
| 906 | emphasis is on FIR assembly rather than individual FIR coefficient identification. | |||
| 866 | 907 | |||
| Our experimental results are very promising in providing a rational approach to selecting | 867 | 908 | Our experimental results are very promising in providing a rational approach to selecting | |
| the coefficients of each FIR filter in the context of a performance target for a chain of | 868 | 909 | the coefficients of each FIR filter in the context of a performance target for a chain of | |
| such filters. The FPGA design that is produced automatically by our | 869 | 910 | such filters. The FPGA design that is produced automatically by the proposed | |
| workflow is able to filter an input signal as expected which validates our model and our approach. | 870 | 911 | workflow is able to filter an input signal as expected, validating experimentally our model and our approach. | |
| We can easily change the quadratic program to adapt it to an other problem. | 871 | 912 | The quadratic program can be adapted it to an other problem based on assembling skeleton blocks. | |
| 872 | 913 | |||
| A perspective is to model and add the decimators to the processing chain to have a classical | 873 | 914 | A perspective is to model and add the decimators to the processing chain to have a classical | |
| FIR filter and decimator. The impact of the decimator is not so trivial, especially in terms of silicon | 874 | 915 | FIR filter and decimator. The impact of the decimator is not trivial, especially in terms of silicon | |
| area for the subsequent stages since some hardware optimization can be applied in | 875 | 916 | area usage for subsequent stages since some hardware optimization can be applied in | |
| this case. | 876 | 917 | this case. | |
| 877 | 918 | |||
| The software used to demonstrate the concepts developed in this paper is based on the | 878 | 919 | The software used to demonstrate the concepts developed in this paper is based on the | |
| CPU-FPGA co-design framework available at \url{https://github.com/oscimp/oscimpDigital}. | 879 | 920 | CPU-FPGA co-design framework available at \url{https://github.com/oscimp/oscimpDigital}. | |
| 880 | 921 | |||
| \section*{Acknowledgement} | 881 | 922 | \section*{Acknowledgement} | |
| 882 | 923 | |||
| This work is supported by the ANR Programme d'Investissement d'Avenir in | 883 | 924 | This work is supported by the ANR Programme d'Investissement d'Avenir in | |
| progress at the Time and Frequency Departments of the FEMTO-ST Institute | 884 | 925 | progress at the Time and Frequency Departments of the FEMTO-ST Institute | |
| (Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e. | 885 | 926 | (Oscillator IMP, First-TF and Refimeve+), and by R\'egion de Franche-Comt\'e. | |
| The authors would like to thank E. Rubiola, F. Vernotte, and G. Cabodevila | 886 | 927 | The authors would like to thank E. Rubiola, F. Vernotte, and G. Cabodevila | |
| for support and fruitful discussions. | 887 | 928 | for support and fruitful discussions. | |
| 888 | 929 | |||
| \bibliographystyle{IEEEtran} | 889 | 930 | \bibliographystyle{IEEEtran} | |
| \balance | 890 | 931 | \balance | |
| \bibliography{references,biblio} | 891 | 932 | \bibliography{references,biblio} | |
| \end{document} | 892 | 933 | \end{document} | |
| 893 | 934 | |||